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[AK8826VN] ms0972-e-01 1 2008/12 general description the ak8826 is a hd/sd tv video encoder with onchip 3-channel 10bit dac. as input data, in sdtv enc oder mode, smte-125m / itur-r.bt601, 656 compat ible y/cb/cr 4:2:2 formats (8bit) are accepted and in hdtv encoder mode, smpte-274m (1080i), smpte296m (720p) compatible y/cb/cr 4:2:2 formats (8bit x 2) are accepted. as input data capture me thod, either a synchronous mode to be made by detecting encoded eav signal or a mode to synchronize with externally-fed h/v sync signal is selectable. outputs of cvbs / sdy / sdc and hdy / hdpb / hdpr and r / g / b analog signal can be output exclusively. vbi signal can be also superimposed on output in addition to video signals by register setting. ak8826 supports i2c compatible interf ace as micro-processor interface. features component video encoder - compatible input data smpte125m-1995 / itu-r bt601 (525i/625i) smpte293m-1996 / itu-r bt1358 (525p/625p) smpte274m-1998 (1080i) smpte296m-2001 (720p) - input signal format (525i / 625i, 525p / 625p, 1080i, 720p) y/cb/cr 4:2:2 (8bit x 1: 525i/625i) y/cb/cr 4:2:2 (8bi t x 2: 525p/625p/1080i/720p) rgb 6:6:6 rgb 5:6:5 - input clock 27mhz (525i / 625i / 525p / 625p) / 74.25mhz (1080i/720p) - output signals y/pb/pr interlace y/pb/pr progressive (eia 770.2, eai 770.3) - input signal synchronization itu-r.bt 656 i/f (eav decode) slave operation by hsync / vsync (525i: itu-r. bt601 compatible 625i / 525p / 625p / 1080i / 720p; cea-861-d compatible) - vbid (cgms-a), cc/xds, wss, cea-805-b (type a/b) - internal color bar generator - internal black burst generator - adjustable y / pb / pr delay function ntsc / pal composite video encoder - ntsc-m, pal-b, d, g, h, i. m, n encoding - composite video output / s-video output - compatible input data smpte125m-1995 / itu-r bt601(525i/ 625i) y/cb/cr 4:2:2 (8bit x 1) rgb 6:6:6 rgb 5:6:5 - input signal synchronization itu-r.bt 656 i/f (eav decode) slave operation by hsync / vsync ( 525i / 625i: itu-r. bt601 compatible) - input clock 27mhz - vbid(cgms-a), cc/xds, wss AK8826VN hd/sd multi format video encoder with 3ch dac
[AK8826VN] ms0972-e-01 2 2008/12 rgb video dac - rgb output - input data format rgb 6:6:6 rgb 5:6:5 - input clock 54mhz (max) common specification - 10bit dac x 3ch (max operating speed 150mhz) - i 2 c bus i/f (400khz) compatible - power down mode - internal vref circuit - 3.0v / 1.8v vcc - 48pin qfn (7.2mm x 7.2mm)
[AK8826VN] ms0972-e-01 3 2008/12 1. block diagram y cb cr y/g cb/b cr/r g b r y/g cb/b cr/r y c cvbs g b r data[17:0] 18-bit clkin sync generator (eav decode or hd/vd sync) hdi vdi ycbcr to rgb rgb to ycbcr selector ycbcr selector ntsc/pal composite video encoder component encoder selector dac1 clock gen pll 74.25mhz-> 148.5mhz 27mhz -> 54mhz delay delay vref u-p i/f buffe r buffe r hdo vdo dac2 dac3 pdn sda scl vref iref bypass hdy/sdy/g hdpb/sdc/b hdpr/cvbs/r test test0 pvdd1 pvdd2 dvdd dvss avdd avss 6.75/13.5/27/54/148.5mhz 27mhz or 74.25mhz sela flt delay rgb test1 tmo fig. 1 block diagram
[AK8826VN] ms0972-e-01 4 2008/12 with register setting, ak8826 works as - multi-format component video encoder (component video encoder) - ntsc/pal composite video encoder (composite video encoder) - high speed video dac 1-1. component video encoder block cb[7:0] 4:2:2 to 4:4:4 x2 interpolation y[9:0] to dac pb[9:0] to dac y[7: 0 cr[7:0] lpf-e x2 lpf-d sync generator hd-timing generator cgms-a wss pr[9:0] to dac fro m clock gen 6.75mhz/13.5/27/54/74.25/148.5mhz fro m timing generato r x2 lpf-f clk rate a clk rate b clk rate b clk rate c x2 lpf-h* x2 lpf-g* *clk rate d sin(x)/x compensation fig. 2 component video encoder block this block described as component video encoder block in this datasheet. clk rate d is only a case of d1(525i/625i) mode. clock rate d1( 525i /625i ) d2( 525p / 625p ) d3/d4(1080i/720p) clk rate a 6.75mhz 13.5mhz 37.125mhz clk rate b 13.5mhz 27mhz 74.25mhz clk rate c 27mhz 54mhz 148.5mhz clk rate d 54mhz - -
[AK8826VN] ms0972-e-01 5 2008/12 1-2. ntsc/pal composite video encoder block cb[7:0] interpolation 4:2:2 to 4:4:4 y[9:0] to dac 13.5mhz c[9:0] to dac y[7:0 cr[7:0] lpf-b dfs sin cos x2 lpf-c u v c x2 lpf-a sync generator sd-timing generator cgms-a wss cvbs[9:0] to dac from clock gen 27mhz from timing generato r sin(x)/x sin(x)/x sin(x)/x 6.75mhz 13.5mhz 27mhz fig. 3 composite video encoder block this block described as composite video encoder block in this datasheet. 1-3 high speed video dac mode ak8826 can be used as high speed video dac. this mode is described as video dac mode in this datasheet. dac1 dac2 data[17:0] dac3 from clkin data distributor level shifter data[5:0] / data[4:0] data[11:6] / data[10:5] data[17:12] / data[15:11] delay (unit clk) hdi vdi delay delay hdo vdo fig. 4 high speed video adc block
[AK8826VN] ms0972-e-01 6 2008/12 1-4. clk gen block clkin 1/2 div 1/4 div x2 clk x1 clk x1/2 clk 1/8 div x1/4 clk x2 pll 74.25 148.5mhz x4 pll 27 108mhz 1/2 div fig. 5 ? clk gen block ? clock rate d1( 525i /625i ) d2( 525p / 625p ) d3/d4(1080i/720p) x1/4 clk 6.75mhz - - x1/2 clk 13.5mhz 13.5mhz 37.125mhz x1 clk 27mhz 27mhz 74.25mhz x2 clk 54mhz 54mhz 148.5mhz
[AK8826VN] ms0972-e-01 7 2008/12 notice information in this document, relations of the word are shown as following table number of lines in frame description in this datasheet 525 interlace 525i or 480i or d1 625 interlace 625i or 576i or d1 525 progressive 525p or 480p or d2 625 progressive 625p or 576p or d2 1125 interlace 1125i or 1080i or d3 750 progressive 750p or 720p or d4
[AK8826VN] ms0972-e-01 8 2008/12 2. ordering guide AK8826VN 48 pin qfn 3. pin assignment 1 2 3 4 10 689 7 51112 20 13 18 17 16 15 14 19 24 22 21 23 27 26 25 30 29 28 33 32 31 36 35 34 41 48 43 44 45 46 47 42 37 39 40 38 test0 iref bvss bypass vref avdd avss daco1 daco2 daco3 flt test1 pdn scl sda pvdd1 sela data0 dvss dvdd data1 data2 data3 data4 data5 data6 data7 data8 data9 data10 pvdd2 dvss data11 data12 data13 tmo vdo hdo clkin hdi vdi data17 pvdd2 data16 dvss dvdd data15 data14 fig. 6 ? pin layout (topview)
[AK8826VN] ms0972-e-01 9 2008/12 4. function of pins pin# pin name power i/o function 1 pdn p1 i control pin for power down and reset. ak8826 is initialized with pdn = low. ak8826 becomes power down states during pdn=low normal operation mode, pdn pin should be high. this pin is prohibited to be hi-z states 2 scl p1 i i2c bus clock input pin. pulled up externally. 3 sda p1 i/o i2c bus data input pin. pulled up externally. 4 pvdd1 p1 p power supply pin for i/o(pdn, sda, scl, sela) 5 sela p1 i i2c bus address select pin. fixed to pvss1 or pvdd1. 6 data0 p2 i data input pin refer ?data input format?. in case of pdn pin = low, hi-z states is possible. 7 dvss d g ground pins for digital. 8 dvdd d p power supply pins for digital. 9 data1 p2 i data input pin refer ?data input format?. in case of pdn pin = low, hi-z states is possible. 10 data2 p2 i data input pin refer ?data input format?. in case of pdn pin = low, hi-z states is possible. 11 data3 p2 i data input pin refer ?data input format?. in case of pdn pin = low, hi-z states is possible. 12 data4 p2 i data input pin refer ?data input format?. in case of pdn pin = low, hi-z states is possible. 13 data5 p2 i data input pin refer ?data input format?. in case of pdn pin = low, hi-z states is possible. 14 data6 p2 i data input pin refer ?data input format?. in case of pdn pin = low, hi-z states is possible. 15 data7 p2 i data input pin refer ?data input format?. in case of pdn pin = low, hi-z states is possible. 16 data8 p2 i/o data input pin refer ?data input format?. in case of pdn pin = low, hi-z states is possible. 17 data9 p2 i/o data input pin refer ?data input format?. in case of pdn pin = low, hi-z states is possible. 18 data10 p2 i/o data input pin refer ?data input format?. in case of pdn pin = low, hi-z states is possible. 19 pvdd2 p2 p power supply pins for i/o(clkin, data[17:0], hdi, vdi) 20 dvss d g ground pins for digital. 21 data11 p2 i/o data input pin refer ?data input format?. in case of pdn pin = low, hi-z states is possible. 22 data12 p2 i/o data input pin refer ?data input format?. in case of pdn pin = low, hi-z states is possible. 23 data13 p2 i/o data input pin refer ?data input format?. in case of pdn pin = low, hi-z states is possible. 24 tmo i/o p2 test pin. leave open. (internally pull-down with approx. 100k-ohm) 25 data14 p2 i/o data input pin refer ?data input format?. in case of pdn pin = low, hi-z states is possible. 26 data15 p2 i/o data input pin refer ?data input format?. in case of pdn pin = low, hi-z states is possible. 27 dvdd d p power supply pins for digital.
[AK8826VN] ms0972-e-01 10 2008/12 28 dvss d g ground pins for digital. 29 data16 p2 i/o data input pin refer ?data input format?. in case of pdn pin = low, hi-z states is possible. 30 pvdd2 p2 p power supply pins for i/o(clkin, data[17:0], hdi, vdi) 31 data17 p2 i/o data input pin refer ?data input format?. in case of pdn pin = low, hi-z states is possible. 32 vdi p2 i/o in case of slave synchronization operation mode, vertical sync timing should be input. in case of pdn pin = low, hi-z states is possible. 33 hdi p2 i/o in case of slave synchronization operation mode, horizontal sync timing should be input. in case of pdn pin = low, hi-z states is possible. 34 clkin p2 i clock input pin composite video encoder mode: input 27mhz clock. component video encoder mode: either 27mhz or 74.25mhz clock is input. (depending on input video format) high speed video dac mode: max input clock is 54mhz. prohibited hi-z states ? 35 hdo p2 o horizontal sync timing signal output pin. in case of pdn pin = low, this pin outputs low. 36 vdo p2 o vertical sync timing signal output pin. in case of pdn pin = low, this pin outputs low. 37 test1 i p2 test pin. connect to dvss. (internally pull-down with approx. 100k-ohm) 38 flt a o filter pin for pll. 4.7nf capacitor and 820-ohm resistor s hould be connected as shown in ?11. system connection example? 39 daco3 a o dac3 output pin. output signal is set by register composite video encoder mode: pr or r component video encoder mode: cvbs high speed video dac mode: depending on input data. load resistor is 300-ohm 40 daco2 a o dac2 output pin. output signal is set by register composite video encoder mode: pb or b component video encoder mode: c high speed video dac mode: depending on input data. load resistor is 300-ohm 41 daco1 a o dac1 output pin. output signal is set by register composite video encoder mode: y or cvbs component video encoder mode: y or g high speed video dac mode: depending on input data. load resistor is 300-ohm 42 avss a g ground pin for analog 43 avdd a p power supply pin for analog. 44 vref a i to be connected to avdd via a 0.1 uf capacitor 45 bypass a o output pin to output on-chip vref voltage. should be connected to avss via a larger-than 0.1 uf capacitor. 46 bvss a g ground pin for substrate. connect to avss. 47 iref a o reference current output pin for dac should be connected to avss via a 3.3 k ohm ( +/- 1 % ) resistor. 48 test0 i p1 test pin. connect to dvss. (internally pull-down with approx. 100k-ohm) power a: avdd d: dvdd p1: pvdd1 p2: pvdd2 i/o: input/output pin i: input pin o: output pin g: ground pin p: power supply pin
[AK8826VN] ms0972-e-01 11 2008/12 pull up / down pins pin name pull-up/down pull-up/down resistor test0 pull down approx. 100k-ohm test1 pull down approx. 100k-ohm tmo pull down approx. 100k-ohm
[AK8826VN] ms0972-e-01 12 2008/12 5. electrical characteristics absolute maximum ratings (* power supply voltages are values where each ground pin(dvss=avss) is at 0v) parameter min. max. unit power supply (vdd) avdd (dac,pll,vref) dvdd (digital core) pdvd1(digital i/o) pvdd2 (digital i/o) -0.3 4.2 2.2 4.2 4.2 v input voltage (vin) -0.3 pvdd1 + 0.3 pvdd2 + 0.3 v input current (iin) +/- 10 ma storage temperature -40 125 c * all power supply ground pins (dvss, avss) should be at the same potential. warning: operation at or beyond these limits may result in permanent da mage to the device. normal operating specifications are not guaranteed at these extremes. recommended operating conditions parameter min. typ. max. unit power supply (vdd) avdd dvdd pvdd1 pvdd2 2.7 1.65 dvdd dvdd 3.0 1.8 1.8 1.8 3.6 2.0 3.6 3.6 v operating temperature (ta) -40 85 c analog characteristics and power dissipation (oper ating voltage avdd3.0v, dvdd 1.8v temperature 25c) parameter min typ. max. unit condition dac resolution 10 bit integral non-linearity error inl +/- 0.6 +/- 2.0 lsb note 1) differential non-linearity error dnl +/- 0.4 +/- 1.0 lsb note 1) output full scale voltage 1.15 1.28 1.41 v load resistor 300 ? dac snr 54 db note 2) output bandwidth +/- 1 db note 3) unbalances between dacs 1.5 3 % note 4) internal reference voltage 1.43 v internal reference drift 60 ppm/c current consumption of analog part 30 40 ma note 5) current consumption of digital part component encoder mode composite encoder mode dac mode 35 8 8 70 16 16 ma note 6) current consumption of sleep mode 1 ma current consumption of power down 10 300 ua pdn=low note 1. dac:148mhz operation note 2. 2mhz sin-wave input. (noise band-width 0 ? 30mhz) note 3. output bandwidth 30mhz: at 148mhz operation dac1 (load resistor 300ohm) channel only ? external load capacitor 10 pf (subaddress[0x0a] hdaflt[1:0]=11) note 4. variation when a 700 mv equivalent code is input on dacs. note 5. dac 3ch on fs=74mhz / component mode (y: 30mhz sin wave, cbcr: 15mhz sin wave) note 6: clock-rate and input data is composite video encoder mode: 515i (27mhz) internal color bar component video encoder mode: 1080i (74mhz) y: 30mhz sin wave, cbcr: 15mhz sin wave) high speed dac mode: 54mhz clock 20mhz sin wave data input.
[AK8826VN] ms0972-e-01 13 2008/12 digital input / output dc characteristics (avdd=2.7-3.6v, dvdd=1.65-2.0v, pvdd1= 1.65- 3.6v, pvdd2 = 1.65-3.6v ta= -40-85c) parameter symbol min typ max unit condition high level input voltage 1 vih1 0.70 pvdd1 v note. 1 high level input voltage 2 vih2 0.70 pvdd2 v note. 2 low level input voltage 1 vil1 0.30 pvdd1 v note. 1 low level input voltage 2 vil2 0.30 pvdd2 v note. 2 high level output voltage voh 0.80 pvdd2 v note. 3 ioh = -600 ua low level output voltage vol 0.20 pvdd2 v note. 3 iol = 1.4 ma input pin leakage current ilikg 10 ua note. 4 i2c high level input voltage vihc 0.77pvdd1 v note. 5 i2c low level input voltage vilc 0.21pvdd1 v note. 5 i2c low level output voltage vol2 0.4 v note. 6 iolc=3ma note. 1. pdn pin. note. 2. clkin, data[17:0], hdi, vdi pins note. 3. hdo, vdo pins note. 4. clkin, data[17:0], hdi, vdi, pdn, sela, sda, scl pins note. 5. sela, sda, scl pins note. 6. sda pin
[AK8826VN] ms0972-e-01 14 2008/12 ac timing ( avdd=2.7-3.6v, dvdd=1.65-2.0v, pvdd1 = dvdd- 3.6v, pvdd2 = dvdd-3.6v ta: -40-85c) (1) clkin (1-1) component video encoder / composite video encoder mode clkin fclk tclkh tclkl vil vih vih,vil w 1/2 ?? fig. 7 parameter symbol min typ max unit note 74.25 74.25 / 74.175mhz clkin fclk 27 mhz 27mhz(*) 4.04 74.25/74.175mhz clkin pulse width h tclkh 15.0 nsec 27mhz 4.04 74.25 / 74.175mhz clkin pulse width l tclkl 15.0 nsec 27mhz (*) accuracy of frequency may affect to color display. (1-2) video dac mode parameter symbol min typ max unit note clkin fclk 6 54 mhz clkin pulse width h tclkh 7.4 nsec clkin pulse width l tclkl 7.4 nsec
[AK8826VN] ms0972-e-01 15 2008/12 (2) pixel data input timing tds tdh data17-data0 hdi vdi clkin vih vil fig. 8 parameter symbol min typ max unit data setup time tds_hd 3.3 nsec data hold time tdh_hd 3.3 nsec note) data17:data0, hdi, vdi can be captured inverted clock edge by resister setting (3) hsync pulse width hdi p hsw fig. 9 parameter symbol min typ max unit note 15 128 d1 video 27mhz 15 64 d2 video 27mhz hsync pulse width phsw 15 272 clks d3, d4 video 74.25mhz (4) pdn pulse width pdn tpdn fig. 10 parameter synbol min typ max unit ?? pdn pulse width tpdn 100 ns
[AK8826VN] ms0972-e-01 16 2008/12 (5) power up sequence there are no order restriction to make power up, avdd, dvdd, pvdd1, pvdd2. clock input is not necessary to write register. (5-1) the sequence for power down mode after power-up. clock input to the clkin pin is necessary to guarantee ?current consumption of power down? (r) : register-bit powe r su pp l y avdd:2.7v dvdd:1.65v pvdd:1.65v pdn clkin pllpdn (r) dtrstn (r) t >100clk convmod[1:0] (r) 0x00 (composite video encoder mode) low t >100ns(note.1) fig. 11 power-up sequence (to make power down state after power-up) note.1) please wait 100ns for make pdn pin low after the voltage of power supply becomes stable enough,
[AK8826VN] ms0972-e-01 17 2008/12 (5-2) setting to composite video encoder mode after power-up after initializing with pdn-pin = low, ak8826 is composite video encoder mode. (r) : register-bit power su pp l y avdd:2.7v dvdd:1.65v pvdd:1.65v pdn clkin pllpdn (r) register set (r) dacnen (r) data convmod[1:0] (r) 0x00 27mhz dtrstn (r) t > 100clk t >100ns t > 30ms (1) (2) (3) fig. 12 power-up sequence (to set composite video encoder mode after power-up) (1) pdn-pin should be low states more than 100ns after power-up. (2) to initialize in composite video encoder block. clock input is ncessary to clkin-pin. dtrstn-bit should be 0 more than 100clock count. (3) bt656 interface mode operation, it is more than 1-frame periode to synchronize with input data. to avoid displaying noise etc, dac should be on after synchronization.
[AK8826VN] ms0972-e-01 18 2008/12 (5-3) setting to component video encoder mode after power-up after initializing with pdn-pin = low, ak8826 is composite video encoder mode. set to component video encoder mode by register setting. (set convmod[1:0]-bit =[01]) (r) shows register-bit convmod[1:0] (r) 0x00 0x01 power su pp l y avdd:2.7v dvdd:1.65v pvdd:1.65v pdn clkin pllpdn (r) register set (r) dacnen (r) data 31 ms 27mhz or 74.25mhz t>100clk t >100ns (1) (2) (3) (5) t>30 ms (6) dtrstn (r) (4) fig. 13 power-up sequence (to set component video encoder mode after power-up) (1) pdn-pin should be low states more than 100ns after power-up. (2) set to component video encoder mode after 100clock count with clock input to clkin-pin. (3) pllpdn-bit should be set to high after setting component video encoder mode. (4) dtrstn-bit shoud be set to high after setting component video encoder mode. (5)(6) after setting pllpdn -bit = high, wait more than 31ms, then set dac on.
[AK8826VN] ms0972-e-01 19 2008/12 (5-4) setting to high speed video dac mode after power-up after initializing with pdn-pin = low, ak8826 is composite video encoder mode. set to component video encoder mode by register setting. (set convmod[1:0]-bit =[10]) (r) shows register-bit power su pp l y avdd:2.7v dvdd:1.65v pvdd:1.65v pdn clkin pllpdn (r) register set (r) dacnen (r) data low 54mhz (max) convmod[1:0] (r) 0x00 0x10 t >100clk t >100ns (1) (2) dtrstn (r) (3) fig. 14 power-up sequence (to set high speed video dac mode after power-up) (1) pdn-pin should be low states more than 100ns after power-up. (2) set to high speed dac mode after 100clock count with clock input to clkin-pin. (3) set to dtrstn-bit should be high after setting high speed video dac mode
[AK8826VN] ms0972-e-01 20 2008/12 (6) power-down sequence and reset sequence after power-down release before setting to pdn=low, dtrstn(r) should be low to initialize. after power-down release (pdn =low -> high), wait for 10ms for analog reference voltage / current becomes stable. during pdn=low (power down states), either with clock-in or clock-not in is during pdn = low, avdd / dvdd can be power-off. power down sequence is shown as fig. 16. (r) means register-bit. pdn = low makes ak8826 initialize condition, so that after power-down release, make sure register setting. (6-1) power-down and power-down release sequence from composite video encoder mode clkin (27mhz) dacnen(r) convmod[1:0](r) 0x00 dtrstn(r) pdn fix to low or high vref 10ms t > 100clk register is initialized, it is necessary to set regsiter again fig. 15 power-down and power-down release sequence from composite video encoder mode
[AK8826VN] ms0972-e-01 21 2008/12 (6-2) power-down and power-down release sequen ce from component video encoder mode ?? clkin 27 or 74.25mhz dacnen(r) pllpdn(r) convmod[1:0](r) 0x01 0x00 dtrstn(r) pdn fix to low or high vref 10ms t > 100clk register is initialized, it is necessary to set regsiter again fig. 16 power-down and power-down release se quence from component video encoder mode (6-3) power-down and power-down release sequence from high speed video dac mode clkin 54mhz (max) dacnen(r) convmod[1:0](r) 0x10 0x00 dtrstn(r) pdn fix to low or high vref 10ms t >100clk fig. 17 power-down and power-down release se quence from component video encoder mode
[AK8826VN] ms0972-e-01 22 2008/12 (7) i 2 c timing (7-1) timing 1 tr tlow sda tbuf thd:sta tf tr tf tsu:sto tsu:sta scl fig. 18 i 2 c timing 1 parameter symbol min max unit bus free time tbuf 1.3 usec hold time (start condition) thd:sta 0.6 usec clock pulse low time tlow 1.3 usec input signal rise time tr 300 nsec input signal fall time tf 300 nsec setup time(start condition) tsu:sta 0.6 usec setup time(stop condition) tsu:sto 0.6 usec ? the above i2c bus related timings are i2c bus s pecifications, and they are not the device limits. for details, refer to i2c bus specifications. (7-2) timing 2 sda thd:dat thigh tsu:dat scl fig. 19 i 2 c timing 2 parameter symbol min max unit data setup time tsu:dat 100 (note1) nsec data hold time thd:dat 0.0 0.9 (note2) usec clock pulse high time thigh 0.6 usec note 1 : when to use in i2c bus standard mode, tsu : dat > = 250 nsec must be satisfied. note 2 : when the ak8826 is used on not-extended tlow bus (used at tlow = minimum specification), this condition must be satisfied. r/w operation to the register is possible without clock input to clkin-pin.
[AK8826VN] ms0972-e-01 23 2008/12 6. common function specification this section describes common function specifications among composite video encoder, component video encoder, high speed video dac function block. device control interface the ak8826 is controlled via i2c bus control interface. [ i2c bus slave address ] i2c slave address is selectable to be either 0x40 or 0x42 by sela pin setting. sela -pin slave address low (pvss1) 0x40 high (pvdd1) 0x42 a6 a5 a4 a3 a2 a1 a0 r/w 0 1 0 0 0 0 sela [ i2c control sequence ] ( 1 ) write sequence when the slave address of the ak8826 write mode is received at th e first byte, sub-address at the second byte and data at the third & succeeding bytes are received. there are 2 operations in write sequence? a sequence to write at every single byte, and a sequential write operation to write multiple bytes successively. (a) single byte write sequence s slave address w a sub address a data a stp 8-bits 1- bit 8-bits 1- bit 8-bits 1- bit (b) multiple byte ( m-bytes ) write sequence ( sequential write operation ) s slave address w a sub address(n) a data(n) a data(n+1) a data(n+m) a stp 8-bits 1 8-bits 1 8-bits 1 8-bits 1 kkk 8-bits 1 (2) read sequence when the slave address of the ak8826 read mode is received at t he first byte, data at the second and succeeding bytes are transmitted from the ak8826. s slave address w a sub address (n) a rs slave address ra data1 a data2 a data3 a kkk data n stp 8-bits 1 8-bits 1 8-bits 1 8-b its 1 8-bits 1 8-bits 1 8-bits 1 abbreviated terms listed above mean : s, rs : start condition a : acknowledge ( sda low ) : not acknowledged ( sda high ) stp : stop condition r / w : 1 : read, 0 : write : to be controlled by the master device. to be output by micro-computer normally. : to be controlled by the slave device. to be output by the ak8826. note: at the mutiplebyte read/write sequence, read or write register operation cannot done at one-time. add[0x00] - add[0x35] operation is done, then add[0x36] - add[0x3f] should be done. to read or to write test register, 1 byte read/write sequence should be done.
[AK8826VN] ms0972-e-01 24 2008/12 mode select ak8826 has 3-function block as composite video encoder, component video encoder and high speed video dac.these functions are selected by convmod[1:0]-bit of i/o data format register (r/w) [sub address 0x0b] . at mode change timing, convmod[1:0]-bit and dacnen-bit of dac control register(r/w) [sub address 0x0d] and pllpdn-bit of powerdown mode register (r/w) [sub address 0x06] should be taken care. i/o data format register sub address 0x0b default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdsdmase yc2rgb reserved dtfmt convmod1 convmod0 inpfmt1 inpfmt0 convmod[1:0]-bit mode note 00 composite video encoder mode component video encoder block becomes power down state automatically. pll block is still working, pllpdn-bit can make pll block to power down state. 01 component video encoder mode composite video encoder block becomes power down states automatically. pllpdn-bit should be set to ?1? for this mode. 10 high speed video dac mode composite/component video encoder block become power down state automatically. pllpdn-bit should be set to ?0? . 11 reserved reserve set dac control register sub address 0x0d default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved olvl dtrstn cvbssel dac3en dac2en dac1en output signal from dac1/2/3 with setting dacnen-bit =1 (n=1,2,3) convmod[1:0]-bit 00 condition cvbssel=0 cvbssel=1 01 dac1 output y cvbs y dac1en=1 dac2 output c - pb dac3 output cvbs - pr in cvbssel=1 case, dac2en -bit and dac3en-bit should be set 0. (output signal from dac2, dac3 is 0 ) powerdown mode register sub address 0x06 < hd block > default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved pllpdn slpen1 slpen0 when setting to component mode, pllpdn-bit should be set to ?1? since x2 pll is necessary to work for component video encoder mode. pllpdn-bit operation 0 pll is power down states 1 pll is working. component video encoder mode, this bit should be set 1.
[AK8826VN] ms0972-e-01 25 2008/12 mode switching sequence (1) component video encoder mode to composite video encoder mode dacnen-bit (r) pllpdn-bit (r) convmod[1:0]-bit (r) 0x00 component video encoder mode composite video encoder mode 0x01 pll is power down state data input input input clkin low or high hdbbg-bit (r) low or high (1) (2) (3) (4) (5) t >30ms (10) dtrstn-bit (r) (9) t >100clk register setting (r) (7) (6) (8) fig. 20 mode switching sequence (component video encoder mode to composite video encoder mode) (1) to avoid making noise, black burst generator is on, then stop inputting data. (2) turn off dacs. (3) black burst generator off. (4) set pllpdn-bit = 0 (pll block becomes power down states) (5) stop clock input to clkin pin. (6) mode change from componet video encoder mode to composite video encoder mode. (7) set sync-mode, output signal etc. (8) chang clock, if necessary. it is allows that changing clock without stopping clock input, however process(6), (7) should be done before clock change. (9) set dtrstn=1 after dtrstn-bit =0. dtrstn-bit =0 periode should be more than 100-clk counts with clock input. (10) turn on dacs after more than 30ms later
[AK8826VN] ms0972-e-01 26 2008/12 (2) composite video encoder mode to component video encoder mode dacnen-bit (r) pllpdn-bit (r) convmod[1:0]-bit (r) 0x01 composite video encoder mode component video encoder mode 0x00 t > 1 ms data input input input clkin low or high sdbb-bit (r) low or high (5) (1) (2) (3) (4) (10) (8) t >30ms (9) register setting (r) (6) (7) fig. 21 mode switching sequence (composite video encoder mode to component video encoder mode) (1) to avoid making noise, black burst generator is on, then stop inputting data. (2) turns off dacs. (3) black burst generator off. (4) stop clock input to clkin pin. (5) mode change from composite video enc oder mode to component video encoder mode. (6) set sync-mode, output signal etc. (7) chang clock, if necessary. it is allows that changing clock without stopping clock input, however process (6), (7) should be done before clock change. (8) after input clock becomes stable, internal pll makes power-up. (pllpdn-bit =1) (9) after pll becomes stable, starting input video data. (10) turn on dacs after more than 30ms later
[AK8826VN] ms0972-e-01 27 2008/12 (3) clock rate change in component video encoder mode fig.23 shows the sequence of clock rate is c hanged from 27mhz to 74.25mhz or 74.25mhz to 27mhz. dacnen-bit (r) pllpdn-bit (r) hdmod[1:0]-bit (r) 27mhz / 74.25mhz mode 74.25mhz / 27mhz mode data input input input clkin low or high hdbb-bit (r) low or high t>1frm (1) (2) (3) (5) (6) (8) (9) t > 1ms (4) (7) d1 or d2 / d3 or d4 d3 or d4 / d1 or d2 27mhz / 74.25mhz 74.25mhz / 27mhz fig. 22 clock rate change in component video encoder mode (1) to avoid making noise, black burst generator is on, then stop inputting data. (2) turns off dacs (3) black burst generator off. (4) set pllpdn-bit = 0 (pll block becomes power down states) (5) mode change, for example, from d1 to d3. (6) chang clock it is allows that changing clock without stopping clock input, however, pllpdn-bit should be 0. (7) turning on pll (set pllpdn-bit = 1) (8) after pll becomes stable, starting input video data. (9) turn on dacs after more than 30ms later
[AK8826VN] ms0972-e-01 28 2008/12 clock input clock is determined by output signal. the relation between input clock and the output signal is defined as following tab le. input clock component video encoder mode ntsc/pal composite video encoder mode d1, d2 d3, d4 high speed video dac mode input clock to clkin pin 27mhz 27mhz 74.25mhz 54mhz (max) dac operation clock rate 27mhz 54mhz 148.5mhz clock to clkin pin internal pll status off on on off d1 = 480i/576i(525i/625i), d2 = 480p/576p (525p/625p), d3 = 1080i (1125i), d4 = 720p (750p) in case of switching clock, pllpdn-bit of powerdown mode register (r/w) [sub address 0x06] should be ?0?. internal pll ak8826 has x2 pll. in case of component video encoder mode, pll should be on. in time to switch clock rate, pllpdn-bit should be ?0?. powerdown mode register sub address 0x06 < hd block > default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved pllpdn slpen1 slpen0 pllpdn function 0 pll is power down 1 pll is working. set pllpdn=1, in case of component video encoder mode. reset (1) component video encoder block and high speed dac block, and serial interface block are reset with making pdn-pin = low. it is not necessary to input clock to clkin pin. (2) composite video encoder block. composite video encoder block is reset under the condition of dtrstn-bit =?0? of dac control register(r/w) [sub address 0x0d] with clock input to clkin-pin. it should be keep dtstn-bit = ?0? at least 100 clock count. dac control register sub address 0x0d default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved olvl dtrstn cvbssel dac3en dac2en dac1en after reset all register values become default value, and video dac output pins become hi-z.
[AK8826VN] ms0972-e-01 29 2008/12 power down it is possible to make ak8826 power down states with pdn-pin = low. power down sequence is defined section (6) power-down sequence and reset sequence after power-down release of ac timing definition. after releasing pdn-pin =low, all register values become default values, it is necessary to set the register again. during pdn pin =low, avdd and dvdd can be power-off with pvdd1and pvdd2=on. sleep mode to set slpen[1:0]-bit of powerdown mode register (r/w) [sub address 0x06] =[11], ak8826 becomes sleep mode. in this mode, all blocks except serial i/f block become power down mode. to save power cons umption much less, use the pdn-pin. sub address 0x06 < hd block > default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved pllpdn slpen1 slpen0
[AK8826VN] ms0972-e-01 30 2008/12 data input format ak8826 supports 4 kinds of data input format such as 8- bit ycbcr / 16-bit ycbcr / 18bit rgb / 16-bit rgb formats. data input format can be defined by inpfmt[1:0]-bit and dtfmt-bit of i/o data format register (r/w). i/o data format register sub address 0x0b default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdsdmase yc2rgb reserved dtfmt convmod1 convmod0 inpfmt1 inpfmt0 inpfmt[1:0] -bits defines bit width. detailed setting is shown in following table inpfmt[1:0]-bit input data format (width) note 00 8-bit data input 01 16-bit data input 10 18-bit data input 11 reserve dtfmt -bit defines data format. dtfmt -bit input data format 0 ycbcr data format 1 rgb data format in case of convmod[1:0]=[00] or [ 01], internal rgb to ycbcr convertor works* * in case of rgb input mode, ak8826 doesn?t support rec.656 i/f mode. * 525i/625i/525p/625p composite, component encode only. convmod[1:0] -bits define encoder mode show as following table. convmod[1:0] -bit mode 00 composite video encoder mode 01 component video encoder mode 10 high speed dac mode 11 prohibited to set rgb to ycbcr data mux dtfmt-bit ycbcr decimation filter cb/cr y mux cb/cr composite video encoder composite video encoder convmod[1:0] -bit video dac mode rgb data formatter inpfmt[1:0] -bit fig. 23 data interface block outline
[AK8826VN] ms0972-e-01 31 2008/12 (1) ycbcr 8bit data input format in case of 525i / 625i data input, this forma is used. data clock is 27mhz. data7-data0 pins are used as data input pins. the order of ycbcr data should be fed cb[7:0] / y[7:0] / cr[7:0] / y[7:0]. yn / cbn / crn means y[n] / cb[n] / cr[n] in following table. d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 - - - - - - - - - - y7 cb7 cr7 y6 cb6 cr6 y5 cb5 cr5 y4 cb4 cr4 y3 cb3 cr3 y2 cb2 cr2 y1 cb1 cr1 y0 cb0 cr0 d17 - d0 corresponds to data17 - data0 pins the register setting is defined as following table. [i/o data fromat register] setting inpfmt[1:0]-bit dtfmt-bit note 00 0 8bit ycbcr data input ? output signal is set convmod[1:0]-bit of i/o data format register (r/w) [sub address 0x0b] and hd mode register (r/w) [sub address 0x00] or sd block control register (r/w) [sub address 0x11] cb y kkk y 2n y 2n+1 y 2n+2 y 2n+3 y 2n+4 kkk kkk cb n cb n+1 cb n+2 kkk cr n cr n+1 cr n+2 clkin (27mhz) data[7:0] fig. 24
[AK8826VN] ms0972-e-01 32 2008/12 (2) ycbcr 16bit data input format in case of 525i / 625i / 525p / 625p / 1080i / 720p data input, this format is used. the relation between input data format and input clock rate to clkin pin are relation as follows, 525i / 625i / 525p / 625p : 27mhz 1080i / 720p / : 74.25mhz data15-data0 pins are used as data input pins. yn / cbn / crn means y[n] / cb[n] / cr[n] in following table. d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 - - cb7 cr7 cb6 cr6 cb5 cr5 cb4 cr4 cb3 cr3 cb2 cr2 cb1 cr1 cb0 cr0 y7 y6 y5 y4 y3 y2 y1 y0 d17 - d0 corresponds to data17 - data0 pins the register setting is defined as following table. [i/o data fromat register] setting inpfmt[1:0]-bit dtfmt-bit note 01 0 16bit ycbcr data input output signal is set convmod[1:0]-bit of i/o data format register (r/w) [sub address 0x0b] and hd mode register (r/w) [sub address 0x00] or sd block control register (r/w) [sub address 0x11] (2-1) 525i / 625i data input clkin (27mhz) data[15:8] y 0 y 3 kkk y 2 kkk kkk cb 0 cr 0 cr 1 cb 1 kkk data[7:0] y 2n+1 y 2n+2 y 2n cb n cr n cb n+1 y 1 fig. 25 (2-2) 525p / 625p / 1080i / 720p data input clkin (27 or 74.25mhz) data[15:8] y 0 y 1 y 3 kkk kkk kkk kkk kkk kkk y 2 kkk kkk kkk kkk cb 0 cr 0 cr 1 cr 2 cb 2 cb 1 y 2n+1 y 2n+3 y 2n+5 y 2n+2 y 2n y 2n+4 cb n cr n cr n+1 cr n+2 cb n+2 cb n+1 kkk kkk data[7:0] fig. 26
[AK8826VN] ms0972-e-01 33 2008/12 (3) rgb 8bit data input format (rgb5:6:5) in case of to encode ntsc/pal composite video signal or ypbpr component video signal from rgb data, this mode is used. clock rate to clkin pin is 27mhz. data7-data0 pins are used as data input pins. input data format is rg[7:0] / gb[7:0] shown as following table. d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 - - - - - - - - - - r4 g2 r3 g1 r2 g0 r1 b4 r0 b3 g5 b2 g4 b1 g3 b0 d17 - d0 corresponds to data17 - data0 pins rg data = [ r4, r3, r2, r1, r0, g5, g4, g3 ] gb data = [ g2, g1, g0, b4, b3, b2, b1, b0 ] the register setting is defined as following table. [i/o data fromat register] setting inpfmt[1:0]-bit dtfmt-bit note 00 1 8bit rgb data input output signal is set convmod[1:0]-bit of i/o data format register (r/w) [sub address 0x0b] and hd mode register (r/w) [sub address 0x00] or sd block control register (r/w) [sub address 0x11] rg0 gb0 gb1 ? gb n gb n+1 kkk kkk ? rg n+1 rg1 rg n clkin (27mhz) data[7:0] kkk kkk kkk kkk kkk fig. 27
[AK8826VN] ms0972-e-01 34 2008/12 (4) rgb 16bit data input format (rgb 5:6:5) in case of encoding ntsc/pal / 525i/625i , 525p/625p component signal, clock rate to clkin pin 27mhz.. using as high speed dac mode, the ma ximum conversion rate is 54mhz. data15 - data0 pins are used as data input pins. d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 - - r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 the register setting is defined as following table. [i/o data fromat register] setting inpfmt[1:0]-bit dtfmt-bit note 01 1 16bit rgb input output signal is set convmod[1:0]-bit of i/o data format register (r/w) [sub address 0x0b] and hd mode register (r/w) [sub address 0x00] or sd block control register (r/w) [sub address 0x11] (4-1) 525i / 625i data input case clkin (27mhz) data[10: 5] b 0 b 0 b 1 b 2 kkk kkk kkk b 2 kkk b 1 kkk kkk kkk kkk g 0 g 0 g 1 g 1 b n b n+1 b n+2 b n+1 b n b n+2 g n g n g n+1 g n+2 g n+2 g n+1 kkk kkk data[4:0] data[15:11] kkk kkk kkk kkk r 0 r 0 r 1 r 1 r n r n r n+1 r n+2 r n+2 r n+1 kkk g 2 g 2 r 2 r 2 fig. 28 (4-2) 525p / 625p data input case clkin (27mhz) data[10: 5] b 0 b 1 b 3 kkk kkk kkk kkk kkk kkk b 2 kkk kkk kkk kkk g 0 g 1 g 3 g 2 b n+1 b n+3 b n+5 b n+2 b n b n+4 g n g n+1 g n+3 g n+5 g n+4 g n+2 kkk kkk data[4:0] data[15:11] kkk kkk kkk kkk r 0 r 0 r 1 r 1 r n r n+1 r n+3 r n+5 r n+4 r n+2 kkk kkk kkk kkk kkk fig. 29
[AK8826VN] ms0972-e-01 35 2008/12 (5) rgb 18bit data input format (rgb 6:6:6 in case of encoding ntsc/pal / 525i/625i , 525p/625p component signal, clock rate to clkin pin 27mhz.. using as high speed dac mode, the ma ximum conversion rate is 54mhz. data17 - data0 pins are used as data input pins. d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 the register setting is defined as following table. [i/o data fromat register] setting inpfmt[1:0]-bit dtfmt-bit note 10 1 18bit rgb input output signal is set convmod[1:0]-bit of i/o data format register (r/w) [sub address 0x0b] and hd mode register (r/w) [sub address 0x00] or sd block control register (r/w) [sub address 0x11] (5-1) 525i / 625i data input case clkin (27mhz) data[11: 6] b 0 b 0 b 1 b 2 kkk kkk kkk b 2 kkk b 1 kkk kkk kkk kkk g 0 g 0 g 1 g 2 g 2 g 1 b n b n+1 b n+2 b n+1 b n b n+2 g n g n g n+1 g n+2 g n+2 g n+1 kkk kkk data[5:0] data[17:12] kkk kkk kkk kkk r 0 r 0 r 1 r 2 r 2 r 1 r n r n r n+1 r n+2 r n+2 r n+1 kkk fig. 30 (5-2) 525p / 625p data input case clkin (27mhz) data[11:6] b 0 b 1 b 3 kkk kkk kkk kkk kkk kkk b 2 kkk kkk kkk kkk g 0 g 1 g 3 g 5 g 4 g 2 b n+1 b n+3 b n+5 b n+2 b n b n+4 g n g n+1 g n+3 g n+5 g n+4 g n+2 kkk kkk data[5:0] data[17:12] kkk kkk kkk kkk r 0 r 1 r 3 r 5 r 4 r 2 r n r n+1 r n+3 r n+5 r n+4 r n+2 kkk fig. 31
[AK8826VN] ms0972-e-01 36 2008/12 on chip out-put limiter ? limiter function is performed on signals which exceed pedestal level. limiter levels are set at ?no limiter?, ?- 1.5ire?, ?- 7ire?. the limit level is set with hdclplvl[1:0]-bit of hd vbi & clip level control register (r/w) [sub address 0x01] in component video encoder mode and sdclplvl[1:0]-bit of sd blo ck delay register (r/w) [sub address 0x13] in composite video encoder mode. hd vbi & clip level control register sub address 0x01 default value 0x04 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdclplvl1 hdclplvl0 reserved reserved reserved hdvunmsk hdvl1 hdvl0 sd block delay register sub address 0x13 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sdclplvl1 sdclplvl0 syd2 syd1 syd0 reserved reserved reserved the limit level defined as this table. hdclplvl[1:0]-bit sdclplvl[1:0]-bit under-shoot limit level 00 no clipping 01 clipped at -7.0 ire level 10 clipped at -1.5 ire level 11 reserved black burst signal generation function the ak8826can output black burst signal (black level output). when hdbbg-bit of hd mode register (r/w) [sub address 0x00] in component video encoder mode, sdbbg-bit of sd block control register (r/w) [sub address 0x11] is set to ?1?, same operation is processed as in the case when the fixed-16 luminance signal and the fixed-cb/cr signal outputs are inpu t. in this case when setup-bit is ?on?, set-up process is done and when it is ?off?, no set-up process is made. hd mode register sub address 0x00 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdcbg hdbbg hdsetup hdeavdec hdcea861 hdmode1 hdmode0 hdrfrsh sd block control register sub address 0x11 default value 0x10 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sdbbg sdcbg sdsetup scr sdvm3 sdvm2 sdvm1 sdvm0
[AK8826VN] ms0972-e-01 37 2008/12 color bar signal generation function the ak8826 can output 100% color bar signal. colo r bar signal is output by setting hdcbg-bit of hd mode register (r/w) [sub address 0x00] in component video encoder mode and sdcbg-bit of sd block control register (r/w) [sub address 0x11] in composite video encoder mode to ?1?. hd mode register sub address 0x00 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdcbg hdbbg hdsetup hdeavdec hdcea861 hdmode1 hdmode0 hdrfrsh sd block control register sub address 0x11 default value 0x10 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sdbbg sdcbg sdsetup scr sdvm3 sdvm2 sdvm1 sdvm0 setup process function in the ak8826, a 7.5% set-up can be added by register. in component video encoder mode, hdsetup-bit of hd mode regist er (r/w) [sub address 0x00] is the control bit of this function and , in composite video encoder mode, sdsetup-bit of sd block control register (r/w) [sub address 0x11] is the control bit of this function this bit is enabled at color-bar generat or mode and black burst generator mode. hd mode register sub address 0x00 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdcbg hdbbg hdsetup hdeavdec hdcea861 hdmode1 hdmode0 hdrfrsh sd block control register sub address 0x11 default value 0x10 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sdbbg sdcbg sdsetup scr sdvm3 sdvm2 sdvm1 sdvm0
[AK8826VN] ms0972-e-01 38 2008/12 closed caption the ak8826 has encoding function of the closed captioning and extended data. on/off control of these functions and its data are in accordance with sd/hd v-blanking control register (r/w) [sub address 0x12] setting. data occupies a consecutive 2byte register area closed caption data 1 register (r/w) [sub address 0x26] closed caption data 2 register (r/w) [sub address 0x27] for closed caption data and cc extended data 1 register (r/w) [sub address 0x28] cc extended data 2 register (r/w) [sub address 0x29] for extended data. data is written at 0x26/0x28(closed caption / ex tended data) first, then 0x27/0x29 in this order data is judged to be updated when data at 0x27 is written. when data is updated, it is encoded on a coming thereafter, pre-scribed line. when no data updating is made, ascii null code is output. each data is assumed with odd parity + 7 bit us asc ii code. parity is processed at the host side. * closed caption data is encoded on the following lines. d1/60 system (smpte) 625/50 system (itu-r) closed caption 21 line default 22 line default extended data 284 line default 335 line default rgb output mode doesn?t support cl osed caption encoding function. 40ir e 50 +/- 2 ir e start parity parity d0-d6 d0-d6 240+/- 48nsec 240+/- 48nsec two 7-bit + parity ascii characters data 10.003 +/- 0.25usec 27.382 usec 33.764 usec 61 usec 10.5 +/- 0.25usec 12.91 usec fig. 32
[AK8826VN] ms0972-e-01 39 2008/12 wss the ak8826 supports to encode wss (itu-r. bt1119), iec62375 whic h distinguish the aspect ratio etc. turning ?on/off? of this function is cont rolled by wssen-bit of sd/hd v-blanking control register (r/w) [sub address 0x12] at composite video encoder mode, hdwss-bit of hd block control register (r/w)[sub address 0x07] . setting data is set to sd wss data 1/2 register(r/w) [sub address 0x18 / 0x19] at composite video encoder mode, and hd wss data 1/2 register (r/w) [sub address 0x08/0x09] at component video encoder mode. sd/hd v-blanking control register sub address 0x12 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved sdwss sdhdcc284 sdhdcc21 sdvbid hd block control register sub address 0x07 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdwss hdcflt1 hdcflt0 hdyflt1 hdyfl t0 reserved colsncen hdvratio wss data up-date timing vsync wss data1 data old data new data i 2 c sda set control register wss data2 fig. 33 wss data1: composite video encoder mode s ubaddress 0x18 / component video encoder mode 0x08 wss data2: composite video encoder mode s ubaddress 0x19 / component video encoder mode 0x09
[AK8826VN] ms0972-e-01 40 2008/12 wss waveform b [us] d [us] e [us] 500mv +/- 5% c [us] a [us] 0 h 44.5 [us] (defined only 625i) fig. 34 encode line encode clock c d e 625i /50hz (itu-r.bt.1119) 23 5mhz (ts=200ns) 11.0 +/- 0.25 27.4 38.4 625p /50hz (iec 62375) 43 10mhz +/- 1khz (ts = 100ns) 5.5 +/- 0.125 13.7 19.2 encode line: 625i/50 23-line / 625p/50 43-line the input video data is not encoded on the wss encoded line. coding: bi-phase modulation coding run-in start code group 1 aspect ratio group 2 enhanced services group 3 subtitles group4 others 29 elements 24 elements 24 elements 24 elements 18 elements 18 elements bit numbering 0 1 2 3 lsb msb 0 : 000111 1 : 111000 bit numbering 4 5 6 7 lsb msb 0 : 000111 1 : 111000 bit numbering 8 9 10 lsb msb 0 : 000111 1 : 111000 bit numbering 11 12 13 lsb msb 0 : 000111 1 : 111000 0x1f1c71c7 0x1e3c1f
[AK8826VN] ms0972-e-01 41 2008/12 video dac the ak8826 has 10-bit resolution, discrete 3 channel current dacs which run at 150mhz. these dacs are designed to output 1.28vo-p full scal e with load resistors of 300-ohm(+/-1.0%) when a 3.9k-ohm(+/-1.0%)resistor is c onnected between iref pin and avss. vref pin should be connected to avdd via 0.1uf ore more capacitor, and bypass pin should be connected to avss via 0.1uf or more capacitor. ( refer to system connection example. ) each dac?s ?on/off? can be individually controlled by dacnen -bit (n=1,2,3) of dac control register [subaddress0x0d]. at the time of dac-off state, the output dac is hi-z. dac control register sub address 0x0d default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved olvl dtrstn cvbssel dac3en dac2en dac1en the relation between dacnen-bit (n=1,2,3) and dac output are shown in following table. dac1en -bit dac2en -bit dac3en -bit 0 1 0 1 0 1 dac1=off dac1=on dac2=off dac2=on dac3=off dac3=on dac setting cvbssel-bit of dac control register(r/w) [sub address 0x0d] sets the output signal from dac1 and dac3. following table shows the output signal and cvbsel-bit. dac control register sub address 0x0d default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved olvl dtrstn cvbssel dac3en dac2en dac1en sd-yc output convmod[1:0]=00 sd-cvbs output convmod[1:0]=00 hd output convmod[1:0]=01 video dac mode convmod[1:0]=10 cvbssel-bit 0 1 0 - dac1 y cvbs y g dac2 c 0-code output pb b dac3 cvbs 0-code output pr r ? hd output: output signal from component video encoder block sd-yc output and sd-cvbs output: output si gnal from composite video encoder block the operation clock of dacs is composite video encoder mode: same clock-rate as the clock fed into clkin-pin. component video encoder mode: x2 clock rate of the clock fed into clkin-pin high speed video dac mode: same clock-rate as the clock fed into clkin-pin.
[AK8826VN] ms0972-e-01 42 2008/12 7. multi-fomat compnent video encoder block block diagram cb[7:0] 4:2:2 to 4:4:4 x2 interpolation y[9:0] to dac pb[9:0] to dac y[7: 0 cr[7:0] lpf-e x2 lpf-d sync generator hd-timing generator cgms-a wss pr[9:0] to dac fro m clock gen 6.75mhz/13.5/27/54/74.25/148.5mhz fro m timing generato r x2 lpf-f clk rate a clk rate b clk rate b clk rate c x2 lpf-h* x2 lpf-g* *clk rate d sin(x)/x compensation fig. 35 component video encoder block
[AK8826VN] ms0972-e-01 43 2008/12 signal process (data path) the output signal can be set with hdrfrsh-bit, hdmode[1:0]-bit of hd mode register [sub address 0x00]. sub address 0x00 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdcbg hdbbg hdsetup hdeavdec hdcea861 hdmode1 hdmode0 hdrfrsh the output signals are defined as following table. output signal hdmode[1:0] -bit hdrfrsh -bit note 525i 00 0 d1/60 625i 00 1 d1/50 525p 01 0 d2/60 625p 01 1 d2/50 1080i / 60 10 0 d3/60 1080i / 50 10 1 d3/50 720p / 60 11 0 d4/60 720p / 50 11 1 d4/50
[AK8826VN] ms0972-e-01 44 2008/12 (1) case of 525i /625i data input y/cb/cr multiplexed data synchronized to 27mhz clock fed into clkin-pin are input. when eav-decoding mode, the timing signal is extracted from data stream. after extrac ting sync-timing, t he y/cb/cr data are proceeded into y-process block and cb/cr -process block. in case of h/v slave operation mode, it is same way as eav sync mode. as shown in the block diagram, y data proceeded by x4 over-sampling filter is added the sync-t iming signal after pass through the delay adjustment block. cb/cr data proceeded by x8 over-sampling f ilter are processed by delay adjustment block. these data are passed to the dac with 54mhz clock rate. demux level conversion 8-bit or 16-bit cb/y/ cr eav decoder mux synchronization mode synchronization timing ydata[9:0] cbdata[ 9:0] crdata[ 9:0] 4:2:2 to 4:4:4 interpolation lpf-e input formatter del ay del ay del ay dac dac dac sync form x2 interpolation lpf-h 27mhz 13.5mhz 27mhz 54mhz x2 interpolation lpf - d x2 interpolation lpf-f x2 interpolation lpf - g fig. 36 525i/625i mode block diagram x4 over-sampling filter for y-data (luminance data) x8 over-sampling filter for cb/cr-data (color data) ? -60 -50 -40 -30 -20 -10 0 10 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0 26.0 frequency[mhz] gain[db] -1.000 -0.800 -0.600 -0.400 -0.200 0.000 0.200 0.00 0.75 1.50 2.25 3.00 3.75 4.50 5.25 6.00 6.75 frequncy[mhz] gain[db} -60 -50 -40 -30 -20 -10 0 10 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 frequency[mhz] gain[db] fig. 37 ? fig. 38 fig. 39
[AK8826VN] ms0972-e-01 45 2008/12 (2) case of 525p/625p data input y/cb/cr data should be input with 16-bit width at 27mhz clock-rate. x2 over-sampling filter for y-data and x4 ove r-sampling filter for cb/cr data is equipped. the block diagram is shown as follows, demux level conversion 8-bit y eav decoder mux synchronization mode synchronization timing y [9:0] cb [9:0] cr [9:0] 4:2:2 to 4:4:4 interpolation lpf-e x2 interpolation lpf-d input formatter delay delay delay dac dac dac sync form x2 interpolation lpf-f 8-bit cb/cr 54mhz 27mhz 27mh z cb/cr y y cb/cr 13.5mhz sin(x)/x compensation fig. 40 525p/625p mode block diagram
[AK8826VN] ms0972-e-01 46 2008/12 over-sampling filter with aperture-effe ct compensation for luminance (525p/625p) ak8826 equips the aperture-effect compensation filter for luminance signal. this filter can be set with hdaft[1:0]-bit of hd block miscellaneous control register [sub address 0x0a] . compensation degree can be set with this register-bit. ?mode 0? is less compensation and ?mode 3? is more compensation. hd block miscellaneous control register sub address 0x0a default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved std770_2c hdcea805b ccwsssue reserved hdaflt1 hdaflt0 default value 0 0 0 0 0 0 0 0 hdaflt[1:0]-bit filter mode note 00 mode0 less 01 mode1 10 mode2 11 mode3 more x2 over-sampling filter for y-data x4 over-sampling filter for cb/cr -60 -50 -40 -30 -20 -10 0 10 0 2 4 6 8 101214161820222426 frequency[mhz] gain[db] aperteu filter -5 -4 -3 -2 -1 0 1 2 3 0510 frequency[mhz] gain[db] mod e0 mod e1 mod e2 mod e3 -60 -50 -40 -30 -20 -10 0 10 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 frequency[mhz] gain[db] fig. 42 x2 over-sampling filter for 525p/625p fig. 41 aperture filter fig. 43 x4 over-sampling filter for 525p/625p
[AK8826VN] ms0972-e-01 47 2008/12 (3) case of 1125i (1080i) 750p(720p) data input y/cb/cr data should be input with 16-bit width at 74.25mhz clock-rate. x2 over-sampling filter for y-data and x4 ove r-sampling filter for cb/cr data is equipped. the block diagram is shown as follows, demux level conversion 8-bit y eav decoder mux synchronization mode synchronization timing y [9:0] cb [9:0] cr [9:0] 4:2:2 to 4:4:4 interpolation lpf-e x2 interpolation input formatter delay delay delay dac dac dac sync form x2 interpolation lpf-f 8-bit cb/cr 148.5mhz 74.25mhz 74.25mh z cb/cr y y cb/cr 37.125mhz sin(x)/x compensation fig. 44 1080i/720p mode block diagram
[AK8826VN] ms0972-e-01 48 2008/12 over-sampling filter with aperture-effect compensation for luminance (1080i/720p) ak8826 equips the aperture-effect compensation filter for luminance signal. this filter can be set with hdaft[1:0]-bit of hd block miscellaneous control register [sub address 0x0a] . compensation degree can be set with this register-bit. ?mode 0? is less compensation and ?mode 3? is more compensation. hd block miscellaneous control register sub address 0x0a default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved std770_2c hdcea805b ccwsssue reserved hdaflt1 hdaflt0 default value 0 0 0 0 0 0 0 0 hdaflt[1:0]-bit filter mode note 00 mode0 01 mode1 10 mode2 11 mode3 x2 over-sampling filter for y-data x4 over-sampling filter for cb/cr -60 -50 -40 -30 -20 -10 0 10 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 frequency[mhz] gain[db] aperteu filter -5 -4 -3 -2 -1 0 1 2 3 010203040 frequency[mhz] gain[db] mod e0 mod e1 mod e2 mod e3 -60 -50 -40 -30 -20 -10 0 10 0 5 10 15 21 26 31 36 frequency[mhz] gain[db] fig. 46 x2 over-sampling filter for 1080i/720p fig. 45 aperture filter fig. 47 x4 over-sampling filter for 1080i/720p
[AK8826VN] ms0972-e-01 49 2008/12 luminance, chrominance band-width limitation filter ak8826 equips band-width limit filter for luminance and chrominance. for luminance, filter is set by hdyflt[1:0]-bit of hd block control register (r/w) [suba ddress 0x07] . for chrominance, filter is set by hdcflt[1:0]-bit of hd block control register (r/w) [sub ad dress 0x07] . hd block control register sub address 0x07 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdwss hdcflt1 hdcflt0 hdyflt1 hdyflt0 reserved colsncen hdvratio hdyflt[1:0] filter note 00 normal default (no limit) 01 mid yflt1 on next page 10 soft yflt2 on next page 11 reserve hdcflt[1:0] filter note 00 normal default (no limit) 01 mid cflt1 on next page 10 soft cflt2 on next page 11 reserve
[AK8826VN] ms0972-e-01 50 2008/12 frequency response of band-width limitation filter the default frequency response (hdyflt [1:0]= 00 / hdcflt [1:0]=00) is shown in the previous section. -60 -50 -40 -30 -20 -10 0 10 0 2 4 6 8 101214161820222426 frequency[mhz] gain[db] yflt1 yflt2 ?????????????? ??????????????? -60 -50 -40 -30 -20 -10 0 10 012345678910111213 frequency[mhz] gain[db] yfl t1 yfl t2 cflt1 cflt2 fig. 49 525i / 625i luminance band-width limitation filter fig. 48 525i / 625i chrominance band-width limitation filter fig. 50 525p / 625p luminance band-width limitation filter fig. 51 525p/ 625p chrominance band-width limitation filter fig. 53 1080i/720p luminance band-width limitation filter fig. 52 1080i/720p chrominance band-width limitation filter -60 -50 -40 -30 -20 -10 0 10 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 frequency[mhz] gain[db] yfl t1 yfl t2 -60 -50 -40 -30 -20 -10 0 10 0 5 10 15 20 25 30 35 frequency[mhz] gain[db] cflt1 cflt2 -60 -50 -40 -30 -20 -10 0 10 0 5 10 15 20 25 frequency[mhz] gain[db] yfl t1 yfl t2 -60 -50 -40 -30 -20 -10 0 10 0 1 2 3 4 5 6 7 8 9 10 11 12 13 frequency[mhz] gain[db] cflt1 cflt2
[AK8826VN] ms0972-e-01 51 2008/12 video interface timing ak8826 has 2 types of video interface, eav decode mode and slave sync mode. interface mode is set by the hdeavdec-bit of hd mode register [sub address 0x00] . hd mode register sub address 0x00 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdcbg hdbbg hdsetup hdeavdec hdcea861 hdmode1 hdmode0 hdrfrsh hdeavdec-bit interface mode note 0 hd/vd slave mode 1 eav decode mode set hdcea861-bit = 0
[AK8826VN] ms0972-e-01 52 2008/12 (1) eav decode mode (1 -1 ) eav decode eav code which is encoded on input dat a stream is decoded, and the device makes synchronization wi th its timing. at the time of 16-bit width data input case, synchroni zation is made with eav of the y7-y0 data, and it is not reference to the eav/sav which are contained in cbcr7-0 data. in case of rgb data input mode, ak8826 doesn?t support this interface mode. eav/sav code those codes succeeding 0xff - 0x00 - 0x00 whic h are fed as input data become eav/sav codes. eav/sav codes have following meani ngs, started with msb. bit number msb lsb word value 7 6 5 4 3 2 1 0 0 0xff 1 1 1 1 1 1 1 1 1 0x00 0 0 0 0 0 0 0 0 2 0x00 0 0 0 0 0 0 0 0 3 0xxx 1 f v h p3 p2 p1 p0 f = 0 : field 1 = 1 : field 2 (f-bit is always 0 in case of progressive data) v = 0 : field blanking (v-blanking) ?? = 1: field blanking (v-blanking) h = 0: sav = 1: eav p3, p2, p1, p0: protection bit following is a relation between protection bit and f/v/h-bit. f v h p3 p2 p1 p0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 0 0 0 1 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1 reference standards input data reference 525i itu-r.bt656 625i itu-r.bt656 525p smpte 293m 625p itu-r. bt1358 1080i smpte 274m 720p smpte 296m
[AK8826VN] ms0972-e-01 53 2008/12 (1-2) synchronization for horizontal direction (eav-sync mode) ak8826 synchronizes with input data horizontally using eav code eav code and horizontal position is shown as following table. 525i (480i) case cb y cr y cb y cr y cb y cr y cb y cr y 359 718 359 719 360 720 360 721 428 856 428 857 0 0 0 1 eav ~~~ sav 625i (576i) case cb y cr y cb y cr y cb y cr y cb y cr y 359 718 359 719 360 720 360 721 431 862 431 863 0 0 0 1 eav ~~~ sav 525p (480p) case y 718 719 720 721 722 723 854 855 856 857 0 1 2 trs eav ~~~ sav 625p (576p) case y 718 719 720 721 722 723 860 861 862 863 0 1 2 trs eav ~~~ sav 1125i (1080i) / 60hz case y 1918 1919 1920 1921 1922 1923 2196 2197 2198 2199 0 1 2 trs eav ~~~ sav 1125i (1080i) / 50hz case y 1918 1919 1920 1921 1922 1923 2636 2637 2638 2639 0 1 2 trs eav ~~~ sav 750p (720p) / 60hz case y 1278 1279 1280 1281 1282 1283 1646 1647 1648 1649 0 1 2 trs eav ~~~ sav 750p (720p) / 50hz case y 1278 1279 1280 1281 1282 1283 1976 1977 1978 1979 0 1 2 trs eav ~~~ sav
[AK8826VN] ms0972-e-01 54 2008/12 (1-3) synchronization for vertical direction (eav-sync mode) the ak8826 makes vertical synchronization (line synchr onization) with either f-bit or v-bit of eav. interlaced signal: using f-bit progressive signal: using v-bit (1-2-1) f-bit relation between f-bit and line-number f-bit 525i 625i 525p/625p 1080i 720p 0 line4 - line265 line1 - line312 line1 - line563 1 line266 - line525 line1 - line3 line313 - line625 all lines f = 0 line564 - line1125 all lines f = 0 (1-2-2) v-bit relation between v-bit and line-number - 525i (480i), 625i (576i), 1080i case field v-bit 525i 625i 1080i (60/50hz) start (v=1) line1 - line19 line624 - line22 line1124 - line1125 - line20 field 1 end (v=0) line20 - line263 line23 - line310 line21 - line560 start (v=1) line264 - line282 line311 - line335 line561 - line583 field 2 end (v=0) line283 - line525 line336 - line623 line584 - line1123 note: ak8826 don?t care v-bit in case of 525i / 625i / 1080i mode - 525p, 625p, 750p case v-bit 525p 625p 720p start (v=1) line1 - line42 line621 - line44 line746 - line750 - line25 end (v=0) line43 - line525 line45 - line625 line26 - line745
[AK8826VN] ms0972-e-01 55 2008/12 (1-4) interlace data and progressive data synchronization (1-4-1) interlace data (525i / 625i / 1080i) when in the interlaced input data cases ( 525i / 625i / 1080i), line synchronization with input data is made with f-bit of eav. digital line-no. f-bit 267 268 269 270 271 272 266 digital line-no. f-bit 4 5 6 7 8 9 3 2 1 265 264 263 fig. 54 525i mode digital line-no. f-bit 314 315 316 317 318 319 313 digital line-no. f-bit 1 2 3 4 5 6 625 624 623 312 311 310 fig. 55 625i mode 1125 1 2 3 4 5 6 1124 digital line-no. f-bit 562 563 564 565 566 567 568 561 digital line-no. f-bit fig. 56 1080i mode
[AK8826VN] ms0972-e-01 56 2008/12 (1-3-2) progressive data (525p / 625p / 720p) when in the progressive data input ca ses, line synchronization with input data is made with v-bit of eav. v-bit 2 1 digital line-no. 6 7 8 9 10 11 12 13 14 ... 40 41 42 525 524 fig. 57 525p case v-bit 622 digital line-no. 6251234567 8 ... 42 43 44 621 620 624 623 45 fig. 58 625p case v-bit digital line-no. 750 1 2 3 4 5 6 7 749 746 745 25 26 fig. 59 720 case
[AK8826VN] ms0972-e-01 57 2008/12 (1-2) eav/sav and data (1-2-1) 525i (t: 13.5mhz) eav sav y 718 719 720 721 722 723 734 735 736 737 856 857 0 1 cb cr 359 360 361 ~~~ 367 368 ~~~ 428 0 16t 122t 50% 50% 0 h 138t fig. 60 clock count between eav to 0th data is 138t. (1-2-2) 625i (t: 13.5mhz) eav sav y 718 719 720 721 722 723 730 731 732 733 862 863 0 1 cb cr 359 360 361 ~~~ 365 366 ~~~ 431 0 12t 132t 50% 50% 0 h 144t fig. 61 clock count between eav to 0th data is 144t.
[AK8826VN] ms0972-e-01 58 2008/12 (1-2-3) 525p (t: 27mhz) eav sav y 718 719 720 721 722 723 ~~~ 734 735 736 737 ~~~ 854 855 856 857 0 1 2 16t 122t 50% 50% 0 h 138t fig. 62 clock count between eav to 0th data is 138t. (1-2-4) 625p (t: 27mhz) eav sav y 718 719 720 721 722 723 ~~~ 730 731 732 733 ~~~ 860 861 862 863 0 1 2 12t 132t 50% 50% 0 h 144t fig. 63 clock count between eav to 0th data is 144t.
[AK8826VN] ms0972-e-01 59 2008/12 (1-2-5) 1080i / 60hz (t: 74.25mhz) eav 0h sav y 1920 1921 1922 1923 1924 2008 ~~~ 2196 2197 2198 2199 0 1 2 88t 188t 50% 50% 4t 192t 280t fig. 64 clock count between eav to 0th data is 280t. (1-2-6) 1080i / 50hz (t: 74.25mhz) eav 0h sav y 1920 1921 1922 1923 1924 2448 ~~~ 2636 2637 2638 2639 0 1 2 528t 188t 50% 50% 4t 192t 720t fig. 65 clock count between eav to 0th data is 720t.
[AK8826VN] ms0972-e-01 60 2008/12 (1-2-7) 720p / 50hz ( t: 74.25mhz) eav 0h sav y 1280 1281 1282 1283 1284 1390 ~~~ 1646 1647 1648 1649 0 1 2 110t 256t 50% 50% 4t 260t 370t fig. 66 clock count between eav to 0th data is 370t. (1-2-8) 750p(720p) / 50hz (t: 74.25mhz) eav 0h sav y 1280 1281 1282 1283 1284 1720 ~~~ 1976 1977 1978 1979 0 1 2 260t 440t 256t 50% 50% 4t 700t fig. 67 clock count between eav to 0th data is 700t.
[AK8826VN] ms0972-e-01 61 2008/12 (1-3) timing for data capture (1-3-1) 525i / 625i 8-bit input mode cb y kkk y 2n y 2n+1 y 2n+2 y 2n+3 y 2n+4 kkk kkk cb n cb n+1 cb n+2 kkk cr n cr n+1 cr n+2 clkin (27mhz) data fig. 68 synchronization code is embedded as follows. clkin (27mhz) 0xx x 0xx x kkk 0xzz 0x00 0xy y yy kkk 0xzz 0x00 cr kkk 0xff cb data eav/sav fig. 69 ?
[AK8826VN] ms0972-e-01 62 2008/12 (1-3-2) 525p / 625p / 1080i / 720p 16-bit data input mode y 0 y 1 y 3 kkk kkk kkk kkk kkk kkk y 2 kkk clkin data kkk kkk kkk cb 0 cr 0 cr 1 cr 2 cb 2 cb 1 y 2n+1 y 2n+3 y 2n+5 y 2n+2 y 2n y 2n+4 cb n cr n cr n+1 cr n+2 cb n+2 cb n+1 kkk kkk fig. 70 synchronization code is embedded in ydata as follows. clkin 0xx x 0xxx kkk 0xff 0x00 y y y kkk 0xzy 0xy y y kkk 0x00 y kkk y_data eav/sav fig. 71
[AK8826VN] ms0972-e-01 63 2008/12 (2) slave synchronization mode ak8826 can make synchronization using hsync/vsync timing. the coming hsync is used for synchronization for horizontally, and vsync is used for line-sync. the falling edge of the each timing signal is used for synchronization. synchronization timing is ak8826 original timing and the timing defined in cea861-d standard. timing is set by the register (hdcea861-bit of hd mode register [sub address 0x00] . hd mode register sub address 0x00 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdcbg hdbbg hdsetup hdeavdec hdcea861 hdmode1 hdmode0 hdrfrsh hdcea861-bit hdcea861d sync-timing note 0 ak8826 sync timing 1 cea-861-d sync-timing the ak8826 recognizes 1st/2nd field to watch the relation between hsync and vsync falling edge.
[AK8826VN] ms0972-e-01 64 2008/12 (2-1) 525i 8-bit x 1ch (based on itu-r .bt.601 standard) (2-1-1) hdcea861-bit = 0 hdi cb 0 y 0 cr 0 y 1 data cb 1 y 2 cr 1 244t (-2t/+1t) 27mhz fig. 72 525i hsync and data (8-bit x 1ch) hdi vdi 4 5 6 7 8 9 10 11 3 digital line-no. fig. 73 525i relation between hsync and vsync (1) hdi vdi 267 268 269 270 271 272 273 274 266 digital line-no. fig. 74 525i relation between hsync and vsync (2) hdi vdi 1/4 h start of 1st field 1/2 h 1/2 h vdi start of 2nd field 1/4 h 1/4 h 1/4 h fig. 75 recognition of field
[AK8826VN] ms0972-e-01 65 2008/12 data enable field 1: 22 vertical blanking lines 240 active vertical lines per field hdi 524 1716clocks 525 2 3 1 5 6 7 8 9 10 11 21 22 261 262 263 38 238 vdi 4 data enable field 2: 23 vertical blanking lines 240 active vertical lines per field hdi 261 1716clocks 262 264 265 263 267 268 269 270271 272 273 284 285 524 525 1 38 238 vdi 266 858 (2-1-2) cea861d-bit = 1 cea 861-d : 525i(480i) / 60hz (hdtv) 720(1440)x480i@59.94/60hz(formats 6 & 7) hdi, vdi input timing line field 1 field 2 fig. 76 fig. 77 fig. 78 1716 total horizontal clocks per line 238 1440 clocks for active video 124 38 114 clocks data enable outside of data enable period y: 10h, cbcr: 80h hdi
[AK8826VN] ms0972-e-01 66 2008/12 (2-2) 625i 8-bit x 1ch (based on itu-r .bt.601) (2-2-1) hdcea861-bit = 0 hdi cb 0 y 0 cr 0 y 1 data cb 1 y 2 cr 1 264t (-2t/+1t) 27mhz fig. 79 625i hsync and data (8-bit x 1ch) hd vd di gi tal line-no. 1 2 3 4 5 6 7 8 625 624 623 622 fig. 80 625i relation between hsync and vsync (1) hd vd digital line-no. 314 315 316 317 318 319 320 313 312 311 310 fig. 81 525i relation between hsync and vsync (2) hdi vdi 1/4 h start of 1st field 1/2 h 1/2 h vdi start of 2nd field 1/4 h 1/4 h 1/4 h fig. 82 recognition of field
[AK8826VN] ms0972-e-01 67 2008/12 data enable field 1: 24 vertical blanking lines 288 active vertical lines per field hdi 623 1728clocks 624 1 2 625 4 5 6 7 8 9 10 22 23 310 311 312 24 264 vdi 3 data enable field 2: 25 vertical blanking lines 288 active vertical lines per field hdi 310 1728clocks 311 313 314 312 316 317 318 319320 321 322 335 336 623 624 625 24 264 vdi 315 864 (2-2-2) hdcea861-bit = 1 cea 861-d : 625i(576i) / 60hz (hdtv) 720(1440)x576i@50hz(formats 21 & 22) hdi and vdi timing line field 1 field 2 fig. 83 fig. 84 fig. 85 1728 total horizontal clocks per line 264 1440 clocks for active video 126 24 138 clocks data enable hdi outside of data enable period y: 10h, cbcr: 80h
[AK8826VN] ms0972-e-01 68 2008/12 ( 2-3 ) 525p 8-bit x 2ch ? (based on smpte 293m) (2-3-1) hdcea861-bit = 0 hdi and vdi timing hdi y 0 y 1 y 2 y 3 data (y) --- y 2n y 2n+1 122t (-2t/+1t) 27mhz cb 0 cr 0 cb 1 cr 1 data (cb/cr) --- cb n cr n fig. 86 525p hsync and data (8-bit x 2ch) hdi vdi 2 1 digital line-no. 6 7 8 9 10 11 12 13 14 15 16 17 18 525 fig. 87 525p relation between hsync and vsync hdi vdi 1/2 h 1/2 h fig. 88 relation between hsync and vsync
[AK8826VN] ms0972-e-01 69 2008/12 data enable) ? progressive frame: 45 vertical blanking lines 480 active vertical lines hdi 522 858clocks 523 525 1 524 7 8 9 10 11 12 13 42 43 522 523 524 525 16 122 vdi (2-3-2) hdcea861-bit = 1 cea 861-d : 525p(480p) / 60hz : hdtv 720x480p@59.94/60hz(formats 2 & 3) hdi and vdi timing line field fig. 89 fig. 90 858 total horizontal clocks per line 122 720 clocks for active video 62 16 60 clocks data enable hdi outside of data enable period y: 10h, cbcr: 80h
[AK8826VN] ms0972-e-01 70 2008/12 ( 2-4 ) 625p 8-bit x 2ch ? (2-4-1) hdcea861-bit = 0 hdi and vdi timing clock count between falling edge of hdi to 0th data is 132t. hdi y 0 y 1 y 2 y 3 y[7:0] --- y 2n y 2n+1 132t 27mhz cb 0 cr 0 cb 1 cr 1 cbcr[7:0] --- cb n cr n fig. 91 625p hsync and data (8-bit x 2ch)
[AK8826VN] ms0972-e-01 71 2008/12 (data enable) progressive frame: 49 vertical blanking lines 576 active vertical lines hdi 620 864clocks 621 624 622 1 2 3 4 5 6 7 44 45 620 621 622 623 12 132 vdi 625 (2-4-2) hdcea861-bit = 1 cea 861-d : 625p(576p) / 50hz : hdtv 720(1440)x576p@50hz(formats 17 & 18) hdi and vdi timing line field fig. 92 fig. 93 864 total horizontal clocks per line 132 720 clocks for active video 64 12 68 clocks data enable hdi outside of data enable period y: 10h, cbcr: 80h
[AK8826VN] ms0972-e-01 72 2008/12 ( 2-5) 1080i / 60hz (8-bit x 2ch) (2-5-1) hdcea861-bit = 0 hdi and vdi timing hdi y 0 y 1 y 2 y 3 data (y) --- y 2n y 2n+1 236t (-2t/+1t) 74.25mhz or 74.25/1.001 cb 0 cr 0 cb 1 cr 1 data (cb/cr) --- cb n cr n fig. 94 1080i hsync and data (8-bit x 2ch) hdi vdi 1125 1 2 3 4 5 6 7 1124 di gi t al li ne-no. fig. 95 1080i relation between hsync and vsync (1) hdi vdi 562 563 564 565 566 567 568 569 561 di gi t al li ne-no. fig. 96 1080i relation between hsync and vsync (2) hdi vdi 1/2 h start of 1st filed 1/2 h 1/2 h vdi start of 2nd field 1/2 h fig. 97 recognition of field
[AK8826VN] ms0972-e-01 73 2008/12 (data enable) field 1: 22 vertical blanking lines 540 active vertical lines per field hdi 1123 2200clocks 1124 1 2 1125 4 5 6 7 8 9 19 20 21 560 561 562 88 192 vdi 3 (data enable) ? field 2: 23 vertical blanking lines 540 active vertical lines per field hdi 560 2200clocks 561 563 564 562 566 567 568 569 570 571 582 583 584 1123 1124 1125 88 192 vdi 565 1100 (2-5-2) hdcea861-bit = 1 cea 861-d : 1080i / 60hz : hdtv 1920x1080i@59.94/60hz(formats 5) hdi and vdi timing line field 1 field 2 fig. 98 fig. 99 fig. 100 2200 total horizontal clocks per line 192 1920 clocks for active video 44 88 148 clocks data enable hdi outside of data enable periode y:10h, cbcr:80h
[AK8826VN] ms0972-e-01 74 2008/12 ( 2-6) 1080i / 50hz (8-bit x 2ch) (2-6-1) hdcea861-bit = 0 hdi and vdi timing hdi y 0 y 1 y 2 y 3 data[7:0] --- y 2n y 2n+1 236t 74.25mhz or 74.25/1.001 cb 0 cr 0 cb 1 cr 1 data[15:8] --- cb n cr n hdi vdi 1125 1 2 3 4 5 6 7 1124 di gi t al li ne-no. hdi vdi 562 563 564 565 566 567 568 569 561 di gi t al li ne-no. 1/2h 1/2h hdi vdi start of 1st field 1/2h vdi start of 2nd field 1/2h fig. 101 1125i(1080i) hsync and data (8-bit x 2ch) fig. 102 1125i (1080i) relation between hsync and vsync(1) fig. 103 1125i (1080i) relation between hsync and vsync(2) fig. 104 field recognition
[AK8826VN] ms0972-e-01 75 2008/12 (data enable) field 2: 23 vertical blanking lines 540 active vertical lines per field hdi 560 2640clocks 561 563 564 562 566 567 568 569 570 571 582 583 584 1123 1124 1125 528 ? ? vdi 565 1320 (2-6-2) hdcea861-bit = 1 eia/cea 861-b : 1080i / 50hz : hdtv 1920x1080i@50hz(formats 20) line field 1 field 2 fig. 105 fig. 106 fig. 107 2640 total horizontal clocks per line 192 1920 clocks for active video 44 528 148 clocks data enable hdi outside of data enable periode y:10h, cbcr:80h (data enable) field 1: 22 vertical blanking lines ? 540 active vertical lines per field ? hdi ? 112 y?*36*2: ? 112 1 2 112 4 5 6 7 8 9 1 2 21 560 ? 561 ? 562 ? ? ? ? ? vdi 3
[AK8826VN] ms0972-e-01 76 2008/12 ( 2-7 ) 720p / 60hz 8-bit x 2ch (2-7-1) hdcea861-bit = 0 hdi y 0 y 1 y 2 y 3 data (y) --- y 2n y 2n+1 300t (-2t/+1t) 74.25mhz or 74.25/1.001 cb 0 cr 0 cb 1 cr 1 data (cb/cr) --- cb n cr n fig. 108 720p hsync and data (8-bit x 2ch hdi vdi 750 1 2 3 4 5 6 7 749 di gi t al li ne-no. fig. 109 720p relatio between hsync and vsync hdi vdi 1/2 h 1/2 h fig. 110 hsync and vsync
[AK8826VN] ms0972-e-01 77 2008/12 (data enable) progressive frame: 30 vertical blanking lines 720 active vertical lines hdi 745 1650clocks 746 748 749 747 1 2 3 4 5 6 24 25 26 745 746 110 260 vdi 750 750 (2-7-1) hdcea861-bit = 1 cea 861-b : 720p / 60hz : hdtv 1280x720p@59.94/60hz(formats 4) line field fig. 111 fig. 112 1650 total horizontal clocks per line 260 1280 clocks for active video 40 110 220 clocks data enable hdi outside of data enable periode y:10h, cbcr:80h
[AK8826VN] ms0972-e-01 78 2008/12 ( 2-8 ) 720p / 50hz 8-bit x 2ch (2-8-1) hdcea861-bit = 0 hdi y 0 y 1 y 2 y 3 data[7:0] --- y 2n y 2n+1 300t 74.25mhz cb 0 cr 0 cb 1 cr 1 data[15:8] --- cb n cr n hdi vdi 750 1 2 3 4 5 6 7 749 di gi t al li ne-no. hdi vdi 1/2 h 1/2 h fig. 113 720p hd and data (8-bit x1ch) fig. 114 720p relation between hdi and vdi fig. 115 hdi vdi input timing
[AK8826VN] ms0972-e-01 79 2008/12 (data enable) progressive frame: 30 vertical blanking lines 720 active vertical lines hdi 745 1980clocks 746 748 749 747 1 2 3 4 5 6 24 25 26 745 746 440 260 vdi 750 750 (2-8-1) hdcea861-bit = 1 cea 861-b : 720p / 50hz : hdtv 1280x720p@50hz(formats 19) line field fig. 116 fig. 117 1980 total horizontal clocks per line 260 1280 clocks for active video 40 440 220 clocks data enable hdi outside of data enable periode y:10h, cbcr:80h
[AK8826VN] ms0972-e-01 80 2008/12 output synchronization waveform ak8826 output synchronization waveform on ys ignal at default, however, colsncen-bit of hd block control register [subaddress 0x27] can add synchronization waveform on not only y-signal but also on pb and pr signal. the synchronization waveform on pb and pr is same as synchronization waveform on y-signal. ? hd block control register sub address 0x07 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdwss hdcflt1 hdcflt0 hdyflt1 hdyflt0 reserved colsncen hdvratio colsncen-bit function 0 sync on y-signal 1 sync on y, pb, pr signal y pb pr y pb pr colsncen-bit = 1 no sync-waveform colsncen-bit = 0 no sync-waveform fig. 118 525i / 625i / 525p / 625p case y pb pr y pb pr colsncen-bit = 1 no sync waveform colsncen-bit = 0 no sync waveform fig. 119 1080i / 720p case
[AK8826VN] ms0972-e-01 81 2008/12 (1) 525i waveform (eia-770.2-c) ? [sync waveform level] only 525i output mode, ak8826 can output both of 286m v sync-waveform and 300mv sync-waveform with setting hdvratio-bit of hd block control register [subaddress0x07] hd block control register sub address 0x07 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdwss hdcflt1 hdcflt0 hdyflt1 hdyflt0 reserved colsncen hdvratio hdvratio-bit sync waveform level 0 300mv (eia770.2-a) 1 286mv (eia770.1-a) (1-1) 525i sync waveform 90% 50% 10% 90% 50% 10% 50% horizontal blanking rise tim e sync rise time h reference to blanking end sync horizontal reference point h blanking start to h-reference 50% 300m v* fig. 120 measurement point value recommended tolerance units total line period(derived) 63.556 usec sync rise time 10% - 90% 140 +/- 20 nsec horizontal sync 50% 4.7 +/- 0.1 usec design spec (t=1/13.5mhz) measurement point reference clock h-blanking start to h-reference 50% 16t h reference to h-blanking end 50% 122t * 286mv sync waveform can be output by register setting.
[AK8826VN] ms0972-e-01 82 2008/12 ? (1-2) 525i frame configuration: vertical sync signal wave form timing 3h 3h 1 2 3 4 5 6 7 89 0.5h 3h 19 +1/- 2line (set by register) 3h 3h 263 264 0.5h 3h 265 266 267 268 269 270 271 272 273 19 283 a b c d e f fig. 121 symbol duration measurement point reference a 429t b 858t c 31t d 429t e 858t f 63t 50% 13.5mhz clock i equalizing pulse serration pulse g h 300mv or 286mv i i i fig. 122 equalizing pulse q serration pulse symbol measurement point value recommended tolerance units field period (derived) 16.6833 msec frame period (derived) 33.3667 msec vertical blanking start before first equalizing pulse 50% 1.5 +/- 0.1 usec vertical blanking (63.556usec x 20lines + 1.5usec) 19* lines + 1.5 usec 0 +/- 0.1 lines usec pre-equalizing duration 3 lines g pre-equalizing pulse width 50% 2.3 +/- 0.1 usec vertical sync duration 3 lines h vertical serration pulse width 50% 4.7 +/- 0.1 usec post-equalizing duration 3 lines g post-equalizing pulse width 50% 2.3 +/- 0.1 usec i sync rise time 140 +/- 20 nsec * there is a case of v-blank of 20 lines. this value is pre-settable by register.
[AK8826VN] ms0972-e-01 83 2008/12 (2) 625i sync-signal (2-1) 625i horizontal sync waveform measurement point value recommended tolerance units total line period(derived) 64.0 usec sync rise time 10% - 90% 0.2 +/- 0.1 usec horizontal sync 50% 4.7 +/- 0.2 usec design spec. (t=1/13.5mhz) measurement point reference clock h-blanking start to h-reference 50% 12t h reference to h-blanking end 50% 132t 90% 50% 10% 90% 50% 10% 50% horizontal blanking rise tim e sync rise time h reference to blanking end sync horizontal reference point h blanking start to h-reference 50% 300m v 700m v fig. 123
[AK8826VN] ms0972-e-01 84 2008/12 (2-2) 625i frame configuration and signal waveform 623 624 625 1 2 3 4 56 0.5h 310 311 0.5h 312 313 314 315 316 317 318 319 320 fig. 124 equalizing pulse serration pulse g h 300mv i i i i fig. 125 equalizing pulse q serration pulse symbol measurement point value recommended tolerance units g pre-equalizing pulse width 50% 2.35 +/- 0.1 usec h vertical serration pulse width 50% 4.7 +/- 0.2 usec g post-equalizing pulse width 50% 2.35 +/- 0.1 usec i sync rise time 200 max300 nsec * there is case where tolerance of sync ri se time is added to pulse width tolerance.
[AK8826VN] ms0972-e-01 85 2008/12 (3) 525p waveform ( eia-770.2-c ) (3-1) 525p horizontal sync waveform 90% 50% 10% 90% 50% 10% 50% horizontal blanking rise tim e sync rise time h reference to blanking end sync horizontal reference point h blanking start to h-reference 300m v fig. 126 measurement point value recommended tolerance units total line period(derived) 31.776 usec sync rise time 10% - 90% 70 +/- 10 nsec horizontal sync 50% 2.33 +/- 0.05 usec
[AK8826VN] ms0972-e-01 86 2008/12 (3-2) 525p vertical sync waveform and timing ak8826 supports both of cea-770.2-a and cea770.2-c hd block miscellaneous control register sub address 0x0a default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved std770_2c hdcea805b ccwsssue reserved hdaflt1 hdaflt0 std770_2c -bit standard remark 0 cea 770.2-a 1 cea 770.2-c (3-2-2) cea 770.2-a (std770_2c-bit =0) 1 6h 6h 6h 14 42 858 795 42 2 6 7 8 12 13 525 43 858 63 795 63 fig. 127 measurement point value recommended tolerance units frame period (derived) 16.6833 msec vertical blanking (31.776usec x 42lines + 0.59usec) 42 lines + 0.59usec 0 +/- 0.05 lines usec vertical sync duration 6 lines vertical serration pulse width 50% 2.33 +/- 0.05 usec (3-2-3) cea 770.2-c (std770_2c-bit =1) 1 9h 6h 6h 17 45 858 795 45 2 9 10 11 15 16 525 46 858 63 795 63 fig. 128 measurement point value recommended tolerance units frame period (derived) 16.6833 msec vertical blanking (31.776usec x 42lines + 0.59usec) 45 lines + 0.59usec 0 +/- 0.05 lines usec vertical sync duration 6 lines vertical serration pulse width 50% 2.33 +/- 0.05 usec
[AK8826VN] ms0972-e-01 87 2008/12 (4) 625p syncronization waveform (itu-r. bt1368) (4-1) 625p horizontal sync waveform 90% 50% 10% 90% 50% 10% 50% e f b d horizontal reference point c 300mv 700mv a fig. 129 symbol characteristics 625/50/1:1 h nominal line period (us) 32 a horizontal blanking interval(us) 6.01.5 d synchronizing pulse (us) 2.350.1 f build-up time (10 to 90%) of the edges of the horizontal synchronizing pulses (us) 0.10.05
[AK8826VN] ms0972-e-01 88 2008/12 (4-2) 625p vertical sync waveform and timing d a b c fig. 130 p r s fig. 131 symbol characteristics 625/50/1:1 v nominal frame period (ms) 20 d vertical blanking interval 49h+ * - build-up time (10 to 90%) of the edges of vertical blanking pulse (us) 0.150.05 a interval between front edges of vertical blanking interval and front edges of first vertical synchronizing pulse 5h* c interval between back edges of last vertical synchronizing pulse and back edge of vertical blanking interval 39h* b duration of sequence of vertical synchronizing pulses 5h* p duration of vertical synchronizing pulse (us) 29.650.1 r interval between vertical synchronizing pulse (us) 2.350.1 s build-up time (10 to 90%) og the vertical synchronizing pulses (us) 0.10.05 * for h and a, see table 1 (itu-r bt.1358) line number 621 1 6 44
[AK8826VN] ms0972-e-01 89 2008/12 (5) 1080i synchronization waveform (eia-770.3-c ) (5-1-1) 1080i horizontal sync waveform (60hz) 50% 45t a (44t) c (44t) 0 h 2200t 1920t eav ancillary data or blanking codew ords sav eav video data 4t 272t 4t 1920t v/2 sm 50% f f b f sp 50% v/2 e (192t) 90% 10% t1 t2 f 300m v 300m v broad pulse blanking bpsrt bpstp hlfp fig. 132 1080i 60hz symbol parameter nominal value reference clock interval tolerance clk tolerance a negative line sync width 0.593 [usec] 44 +/- 3 +/- 0.040 [usec] b end of active video 1.120 [usec] 89 +0.080 [usec] c positive line sync width 0.593 [usec] 44 +/- 3 +/- 0.040 [usec] e start of active video 2.589 [usec] 192 -0 / + 6 +0.080 [usec] f rise/fall time 0.054 [usec] 4 +/- 1.5 +/- 0.020 [usec] t2 ? t1 symmetry of rising edge - - +/- 0.002 [usec] sm amplitude of negative pulse 300 [mv] - +/- 6mv sp amplitude of positive pulse 300 [mv] - +/- 6mv v amplitude of video signal 700 [mv] - total lines 2200 active lines 1920 -12, +0 bpsrt broad pulse start pos 132 -3 ~ +3 bpstp broad pulse stop pos 1012 -3 ~ +3 hlfp h/2 pos 1100 -3 ~ +3
[AK8826VN] ms0972-e-01 90 2008/12 (5-1-2) 1080i vertical sync waveform and timing (60hz) frame configuration 5h 20h 22h 1123 1124 1125 1 2 3 4 5 6 7 8.... 8.... 20 21 5h 5h 20.5h 23h 560 561 562 563 564 565 566 567 568 569 570... 583 584 fi rst fi el d second fi el d fig. 133 vertical sync waveform (refer to itu-r.bt709) 0 h 1h 300mv 300mv fig. 134 duration tolerance 132 t +/- 3 1100 t +/- 3 1012 t +/- 3
[AK8826VN] ms0972-e-01 91 2008/12 (5-2-1) 1080i horizontal sync waveform (50hz) 50% 485t a (44t) c (44t) 0 h 2640t 1920t eav ancillary data or blanking codew ords sav eav video data 4t 712t 4t 1920t v/2 sm 50% f f b f sp 50% v/2 e (192t) 90% 10% t1 t2 f 300m v 300m v broad pulse blanking bpsrt bpstp hlfp fig. 135 1080i 60hz symbol parameter nominal value reference clock interval tolerance clk tolerance a negative line sync width 0.593 [usec] 44 +/- 3 +/- 0.040 [usec] b end of active video 7.120 [usec] 529 +0.080 [usec] c positive line sync width 0.593 [usec] 44 +/- 3 +/- 0.040 [usec] e start of active video 2.589 [usec] 192 -0 / + 6 +0.080 [usec] f rise/fall time 0.054 [usec] 4 +/- 1.5 +/- 0.020 [usec] t2 ? t1 symmetry of rising edge - - +/- 0.002 [usec] sm amplitude of negative pulse 300 [mv] - +/- 6mv sp amplitude of positive pulse 300 [mv] - +/- 6mv v amplitude of video signal 700 [mv] - total lines 2640 active lines 1920 -12, +0 bpsrt broad pulse start pos 132 -3 ~ +3 bpstp broad pulse stop pos 1012 -3 ~ +3 hlfp h/2 pos 1100 -3 ~ +3
[AK8826VN] ms0972-e-01 92 2008/12 (5-2-2) 1080i vertical sync waveform(50hz) 5h 20h 22h 1123 1124 1125 1 2 3 4 5 6 7 8.... 8.... 20 21 5h 5h 20.5h 23h 560 561 562 563 564 565 566 567 568 569 570... 583 584 fi rst fi el d second fi el d fig. 136 vertical sync waveform (refer to itu-r.bt709 standard) 0 h 1h 300mv 300mv fig. 137 duration tolerance 132 t +/- 3 1100 t +/- 3 1012 t +/- 3
[AK8826VN] ms0972-e-01 93 2008/12 (6) 720p synchronization waveform and timing (eia-770.3-c ) ? (6-1-1) 720p horizontal sync waveform (60hz) 50% 70t a (40t) c (40t) 0 h 1650t 1280t eav ancillary data or blanking codew ords sav eav video data 4t 362t 4t 1280t v/2 sm 50% f f b f sp 50% v/2 e (260t) 90% 10% t1 t2 f 300m v 300m v broad pulse blanking bpsrt bpstp fig. 138 symbol parameter nominal value reference clock interval tolerance clk tolerance a negative line sync width 0.539 [usec] 40 +/- 3 +/- 0.040 [usec] b end of active video 1.495 [usec] 111 +0.080 [usec] c positive line sync width 0.539 [usec] 40 +/- 3 +/- 0.040 [usec] e start of active video 3.502 [usec] 260 -0 / + 6 +0.080 [usec] f rise/fall time 0.054 [usec] 4 +/- 1.5 +/- 0.020 [usec] t2 ? t1 symmetry of rising edge - - +/- 0.002 [usec] sm amplitude of negative pulse 300 [mv] - +/- 6mv sp amplitude of positive pulse 300 [mv] - +/- 6mv v amplitude of video signal 700 [mv] - total lines 1650 active lines 1280 -12, +0 bpsrt broad pulse start pos 260 0 ~ +6 +0.080 [usec] bpstp broad pulse stop pos 1540 -6 ~ 0 - 0.080 [usec]
[AK8826VN] ms0972-e-01 94 2008/12 (6-1-2) 720p vertical sync waveform (60hz) (refer to eia-770.3-c) 5h 25h 30h 745 746... 750 1 2 3 4 5 6 7 8.... 8.... 25 26 fig. 139 0 h 1h 300mv 300mv fig. 140 duration tolerance 260 t -0 / +6 1540t -6 / +0
[AK8826VN] ms0972-e-01 95 2008/12 (6) 720p synchronization waveform ( eia-770.3-c ) ? (6-1-1) 720p horizontal sync waveform (50hz) (based on smpte296m 50% 70t a (40t) c (40t) 0 h 1650t 1280t eav ancillary data or blanking codew ords sav eav video data 4t 362t 4t 1280t v/2 sm 50% f f b f sp 50% v/2 e (260t) 90% 10% t1 t2 f 300m v 300m v broad pulse blanking bpsrt bpstp fig. 141 symbol parameter nominal value reference clock interval tolerance clk tolerance a negative line sync width 0.539 [usec] 40 +/- 3 +/- 0.040 [usec] b end of active video 5.926 [usec] 440 c positive line sync width 0.539 [usec] 40 +/- 3 +/- 0.040 [usec] e start of active video 3.502 [usec] 260 -0 / +6 +0.080 [usec] f rise/fall time 0.054 [usec] 4 +/- 1.5 +/- 0.020 [usec] t2 ? t1 symmetry of rising edge - - sm amplitude of negative pulse 300 [mv] - sp amplitude of positive pulse 300 [mv] - v amplitude of video signal 700 [mv] - total lines 1980 active lines 1280 bpsrt broad pulse start pos 260 0 ~ +6 +0.080 [usec] bpstp broad pulse stop pos 1540 -6 ~ 0 - 0.080 [usec]
[AK8826VN] ms0972-e-01 96 2008/12 v-blank interval the ak8826 has functions to set v-blank interval and to control output mode during the v-blank interval. v-blank interval is set by hdvl[1:0]0bit of hd vbi & chip level control register [subaddress 0x01] . the output mode during v-blank interval set by vunmask-bit. hd vbi & clip level control register sub address 0x01 default value 0x04 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdclplvl1 hdclplvl0 reserved reserved reserved hdvunmsk hdvl1 hdvl0 v-blank interval setting hdvl[1:0]-bit 10 11 00 01 525i line1 ? line18 line264 ? line281 line1 ? line19 line264 ? line282 line1 ? line20 line264 ? line283 line1 ? line21 line264 ? line284 625i line623 ? line20 line311 ? line333 line623 ? line21 line311 ? line334 line623 ? line22 line311 ? line335 line623 ? line23 line311 ? line336 525p line1 ? line40 line1 ? line41 line1 ? line42 line1 ? line43 625p line621 ? line42 line621 ? line43 line621 ? line44 line621 ? line45 1080i line1124 ? line1125 line1 ? line18 line561 ? line581 line1124 ? line1125 line1 ? line19 line561 ? line582 line1124 ? line1125 line1 ? line20 line561 ? line583 line1124 ? line1125 line1 ? line21 line561 ? line584 720p line746 ? line750 line1 ? line23 line746 ? line750 line1 ? line24 line746 ? line750 line1 ? line25 line746 ? line750 line1 ? line26 the relation between b-blank interval and hdvunmask-bit are shown as following table mode hdvunmsk 525i/625i mode 525p/625p mode 1080i mode 720p mode 0 blank level output during v-blank interval blank level output during v-blank interval blank level output during v-blank interval blank level output during v-blank interval 1 input data is output even during v-blank interval (525i : line1-9 & line264-272 625i : line623-7 & line311-318 are excluded) input data is output even during v-blank interval ( 525p : line1-12 625p : line641-5 are excluded ) input data is output even during v-blank interval (line1124-1125-6 & line561-568 are excluded) input data is output even during v-blank interval (line746-750-5 are excluded )
[AK8826VN] ms0972-e-01 97 2008/12 adjustable timing function between sync signal and hdy signal, between hdpb signal and hdpr signal sync timing and y signal output relation is adjustable in the ak8826. setting of adjustable amount is made by hdydelay[2:0]-bit of hdypbpr delay control register [subaddress 0x02]. adjustable range between sync signal and y signal is +/- 3clocks. adjustable unit in 525i / p mode is based on 27mhz clo ck and in 1080i/720p modes it is based on 74.25mhz clock. by this bit manipulation, pb/pr are shifted similarly as in the case of y. pb / pr signals with y signal relation are adjusted by pbprde lay[2:0]-bit of hdypbpr delay control register [subaddress0x02]. adjustable range is +/- 3clocks. adjustable unit in 525i / p m odes is based on 27mhz clock, and in 080i/720p modes, it is based on 74.25mhz. y 3clk 3clk 27mhz-clock pb/pr y signal and pbpr signal relation 241t @ 27mhz y (default) 244t @ 27mhz y 247t @ 27mhz sync signal and y signal relation fig. 142 525i/p, 625i/p mode y 3clk 3clk 74.25mhz-clock pb/pr y signal and pbpr signal relation 185t @ 74.25mhz y (default) 188t @ 74.25mhz y 191t @ 74.25mhz sync signal and y signal relation fig. 143 1080i mode
[AK8826VN] ms0972-e-01 98 2008/12 y 3clk 3clk 74.25mhz-clock pb/pr y signal and pbpr signal relation 253t @ 74.25mhz y (default) 256t @ 74.25mhz y 259t @ 74.25mhz sync signal and y signal relation fig. 144 720p mode
[AK8826VN] ms0972-e-01 99 2008/12 analog rgb signal output rgb conversion ( 601 color space and always sync-on-green(sog) ) is possible only with 525i / 625i or sdtv input. conversion factors r = y + 1.372 * ( cr + 128 ) g = y + 0.336 * ( cb + 128 ) + 0.698 * ( cr + 128 ) b = y + 1.732 * ( cb + 128 ) rgb signals are output at the same timing as in ypbpr conversion and their levels are rgb matrix results. a similar sync signal is carried out on g signal. the ak8826 outputs rgb signal by setting yc2rgb-bit of i/o data format register. i/o data format register sub address 0x0b default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdsdmase yc2rgb reserved dtfmt convmod1 co nvmod0 inpfmt1 inpfmt0 input data input data analog rgb output yc2rgb-bit ycbcr data 1 rgb data* 0 * ak8826 doesn?t support eav decode interface mode in case of rgb data in.
[AK8826VN] ms0972-e-01 100 2008/12 video id (cea-805-a / cea-805-b) the ak8826 has a function to super impose a copy protect information cgms-a on output signal. the ak8826 supports both of cea-805-a and cea-805-b standards. (1) cea-805-a 0 700mv 70% -300mv ref bit1 bit2 bit3 bit20 b c a h : white peak (70+/- 10)% l : 0 (+10 / - 5) % 0 h fig. 145 a b c line 525i* (480i) 11.2 +/- 0.3usec (time from 0h) 2.235 +/- 50nsec 49.1 +/- 0.44usec line 20 line 283 525p* (480p) 6t (5.8 +/- 0.15usec) (time from 0h) t +/- 30nsec 22t (21.2 +/- 0.22usec) t : 1/(f h x 33) = 963nsec line 41 1080i 4t ( 4.15 +/- 0.16usec) t +/- 30nsec 22t ( 22.84 +/- 0.21usec) t : 1/(f h x 2200/77) = 1.038usec line 19 line 582 720p 4t (3.13 +/- 0.09usec) t +/- 30nsec 22t (17.20+/- 0.16usec) t : 1/(f h x 1650/58) = 0.782usec line 24 * sync signal waveform of 525i/p signals differ from the above, but timing is defined based on 0h point as starting point (time from 0h). bit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 data word 0 2bits word 1 4bits word 2 8bits crcc 6bits 20 bit data is configured with wrod 0: 2bits / wrod 1: 4 bits / word 2: 8 bits / crcc: 6 bits, as shown above. when to set cgms-a data, set hdvbiden-bit of hd vbid data 1 register [subaddress 0x03 ] to ?1?, and write a setting value to hd vbid data 1/2 register[subaddress 0x03/0x04] . hd vbid data 1 register address 0x03 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdvbiden reserved hdvbid1 hdvbid2 hdvbid3 hdvbid4 hdvbid5 hdvbid6 hd vbid data 2 register address 0x04 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdvbid7 hdvbid8 hdvbid9 hdvbid10 hdvbid11 hdvbid12 hdvbid13 hdvbid14
[AK8826VN] ms0972-e-01 101 2008/12 cgms-a data should be finished being writt en 1-line before of the target lines. 525i: line20 / line283 525p: line41 1080i: line19 / line582 720p: line24 i 2 c write cgms-a data out data(n) fig. 146 crcc is automatically calc ulated and added in the ak8826. default value of ?crcc polynomial expressed x6+x+1? are all ones (see diagram bellow) d d d d d d sw2 sw1 output inpu t b a fig. 147 crcc generation is made as follows - set default values to all ones and closed sw1. set sw2 to ?a? position and first 14bit data is input, then at the 15th bit open sw1 and set sw2 to ?b? position, and crcc is output. when cgms-a output and other signal wa veforms coincide, cgms-a precedes.
[AK8826VN] ms0972-e-01 102 2008/12 (2) cea-805-b this standard is adopted to 480p / 1080i / 720p output mode. c ea805-b type-a standard is same as cea-805-a standard. 0 700mv 70% -300mv b a h : white peak (70+/- 10)% l : 0 (+10 / - 5) % 0 h h5 p5 p 6 p7 p8 ? ? ? p126 p127 b b b s sb : star symbol p0 p 1 p2 p3 p4 h4 h3 h2 h1 h0 fig. 148 a b tolerance form 0h line 480p* 1 156t (time from 0h) 4t +/- 18.5ns t : 1/27mhz line 43 1080i 308t 10t +/- 18.5ns t : 1/74.25mhz line 18 line 581 720p 232t* 2 8t +/- 18.5ns t : 1/74.25mhz line 23 *1 sync signal waveform of 480p differ from the above, but timing is defined based on 0h point as starting points. *2 position of 232t is the position before starting active video area. when to set cea-805-b typeb data, set hdcea805b-bit of hd block miscellaneous control register[subaddress 0x0a] to ?1?, and write a setting value to vbid-b header data register/vbid vers ion number register/vbid payload packet length register/vbid-b dat a1/2/3/4/5/6/7/ 8/9/10/11/12/13 re gister {subaddress 0x40 - 0x50} crcc is automatically calcul ated and added in the ak8826. default values of ?crcc polynomial expressi on x6+x+1? are all ones (see diagram bellows) d d d d d d sw2 sw1 output inpu t b a fig. 149
[AK8826VN] ms0972-e-01 103 2008/12 closed caption the description about ?closed caption? is wri tten in [6. common function specification]. closed caption function is valid at 525i mode. wss the description about ?wss? is written in [6. common function specification]. wss function is valid at 625i /625p mode. rgb output the ak8826 can output analog rgb signal with digital rgb data in. yc2rgb-bit of i/o data format register [subaddress 0x0b] is a control bit for rgb output function. ? i/o data format register sub address 0x0b default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdsdmase yc2rgb reserved dtfmt convmod1 co nvmod0 inpfmt1 inpfmt0 yc2rgb-bit output signal note 0 yuv output 1 rgb output dac operating clock the ak8826 has x2 pll, dac works with this x2 clo ck in component video encoder mode. following table shows dac operation clock of each mode. input data 525i/625i 525p/625p 1080i 720p dac operation clock 54mhz 54mhz 148.5mhz 148.5mhz
[AK8826VN] ms0972-e-01 104 2008/12 8. composite video encoder block block diagram cb[7:0] 4:2:2 to 4:4:4 y[9:0] to dac 13.5mhz c[9:0] to dac y[7:0 cr[7:0] lpf-b dfs sin cos x2 lpf-c u v c x2 lpf-a sync generator sd-timing generator cgms-a wss cvbs[9:0] to dac from clock gen 27mhz fro m timing generato r sin(x)/x sin(x)/x sin(x)/x 6.75mhz 13.5mhz 27mhz fig. 150 composite video encoder block diagram
[AK8826VN] ms0972-e-01 105 2008/12 setting of output signal sdvm[3:0]-bit of sd block control register [subaddress0x11] defines the output signal from the ak8826. sd block control register sub address 0x11 default value 0x10 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sdbbg sdcbg sdsetup scr sdvm3 sdvm2 sdvm1 sdvm0 table of the relation between output signal and sdvm[3:0]-bit sdvm0 sdvm1 sdvm2 sdvm3 scr note ntsc 0 0 0 0 1 setup-bit should be set, if it is necessary ntsc-4.43 1 1 0 0 0 pal 1 1 1 1 1 pal-m 1 0 1 0 1 pal-60 1 1 1 0 0 pal-nc 0 1 1 1 1
[AK8826VN] ms0972-e-01 106 2008/12 video signal filter (1) luminance filter luminance filter of composite video encoder can be selectable by register setting. register-bit for filter setting is sd bloc k flt register(r/w) sdylft[1:0]-bit. sd block flt register sub address 0x14 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved sdyflt1 sdyflt0 reserved reserved reserved sdyflt [1:0] -bit selected filter note 00 yflt0 default 01 yflt1 10 yflt2 ? characteristics of each filter are shown as fig. 152. ? -60 -50 -40 -30 -20 -10 0 10 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 frequency[mhz] gain[db] yflt0 yflt1 yflt2 fig. 151 lpf-a
[AK8826VN] ms0972-e-01 107 2008/12 (2) chrominance filter (2-1) over-sampling filter(6.75mhz -> 13.5mhz) for cb /cr data in composite video encoder block. (lpf-b) frequency response of this filter is shown as fig. 153 (2-2) over-sampling filter(6.75mhz -> 13.5mhz) for c data in composite video encoder block. (lpf-c) frequency response of this filter is shown as fig. 154 -60 -50 -40 -30 -20 -10 0 10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 frequency[mhz] gain[db] -60 -50 -40 -30 -20 -10 0 10 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 frequency[mhz] gain[db] fig. 152 lpf-b frequency response fig. 153 lpf-c frequency response
[AK8826VN] ms0972-e-01 108 2008/12 color burst signal (sdtv) color burst signal is generated by 32bits-length digital frequency synthesizer. subcarrier frequency of color-burst is set b y sdvm0-sdvm1 -bits of sd block control register (r/w) [sub address 0x11] . sd block control register sub address 0x11 default value 0x10 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sdbbg sdcbg sdsetup scr sdvm3 sdvm2 sdvm1 sdvm0 burst table sub-carrier frequency 3.57561188mhz is allowed when pal-m mode is selected. sub carrier frequency and sub carrier phase are set by sub carrier frequency control register (r/w) [sub address 0x16] sub carrier phase control register (r/w) [sub address 0x17] . the burst frequency and initial phase resolution are as follows. frequency resolution 0.8046hz sch phase resolution 360 /256 standard subcarrier freq (mhz) video process 1 [sdvm1,sdvm0] ntsc-m 3.57954545 [0,0] pal-m 3.57561188 [0,1] pal-b,d,g,h,i 4.43361875 [1,1] pal-n(arg) 3.5820558 [1,0] pal-n(non-arg) 4.43361875 [1,1] pal60 4.43361875 [1,1] ntsc-4.43 4.43361875 [1,1]
[AK8826VN] ms0972-e-01 109 2008/12 video interface timing (composite video encoder block) to synchronize with input data, ak8826 supports two kinds of interface mode. (1) itu-r bt.656 interface mode (2) slave operation with hd/vd interface mode this interface mode is set by rec656-bit of sd blanking set register (r/w) [sub address 0x10] . sd blanking set register sub address 0x10 default value 0xa1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sdbln4 sdbln3 sdbln2 sdbln1 sdbln0 reserved reserved rec656 rec656-bit interface mode note 0 slave operation with hd/vd 1 itu-r.bt656 i/f mode (1) itu-r bt.656 i/f mode when ak8826 receives itu-r bt. 656 signal, ak8826 decodes [eav] code in the data for sync hronization then outputs the hsync. ak8826 outputs hsync at the rising edge of sysclk in the timing of the 32nd/24th (ntsc/pal) data slot, which is counted from the [eav] st arting point as below. rec656-bit=1 of sd blanking set register (r/w) [sub address 0x10] should be ?0? for setting to this mode. ? eav sav ??? y/ cb/ cr cb y cr y cb y cr y cb y cr y cb y cr y cb y cr y cb data# 525 system 360 720 360 721 361 722 361 723 368 736 368 855 428 856 428 857 0 0 0 1 1 data# 625 system 360 720 360 721 361 722 361 723 366 732 366 861 431 862 431 863 0 0 0 1 1 33 / 25t (525 / 625) 243 / 263t (525 / 625) ? clki n hdi analog out 276/ 288t (525 / 625) fig. 154
[AK8826VN] ms0972-e-01 110 2008/12 (2) slave mode on slave mode operation, hsy nc and vsync are input to ak8826. ak8826 monitors the transition of hsy nc at the timing of the rising edge of sysclk. after ak8826 recognizes hsync is low-logic, ak8826 sets the slot number to the 32nd/24th (ntsc/pal), internally, then ak8826 starts to sample the data as cb on 276th/288th (ntsc/pal) slot. video field is recognized the transiti on timing between vsync and hsync. as in t he figure, there is a tolerance of 1/4h. this interface mode is set by rec656-bit =0 of sd blanking set register (r/w) [sub address 0x10] . hdi cb 0 y 0 cr 0 y 1 data cb 1 y 2 cr 1 244t / 264t (525/625) 27mhz fig. 155 relation between hsync and data field detection with hsync and vsync 1/4 h hdi vdi 1st field 1/2 h 1/2 h vdi 2nd field 1/4 h 1/4 h 1/4 h fig. 156 hd/vd timing
[AK8826VN] ms0972-e-01 111 2008/12 relation between line# and vd is shown as fig.158 ? 525-line system hdi vdi di gi tal line-no. 4 5 6 7 8 9 10 11 3 2 1 525 fig. 157 1st field hdi vdi 267 268 269 270 271 272 273 274 266 di gi tal line-no. 265 264 263 262 fig. 158 2nd field 625 line system hdi vdi di gi tal line-no. 1 2 3 4 5 6 7 8 625 624 623 622 fig. 159 1st field hdi vdi digital line-no. 314 315 316 317 318 319 320 313 312 311 310 fig. 160 2nd field
[AK8826VN] ms0972-e-01 112 2008/12 sync signal waveform, burst waveform (sd) (1-1) ntsc / ntsc-4.43 / pal-m( sd block control register [sdvm3:sdvm2]-bit = 00 / 01 w ? ) smpte-170m 90% 50% 10% 90% 50% 10% 50% horizontal blanking rise tim e sync rise time h reference to blanking end sync horizontal reference point h blanking start to h -reference 50% sync level 90% 10% h . re f. to b u rst sta rt burst envelope rise tim e 50% burst height burst fig. 161 measurement point value recommended tolerance units total line period(derived) 63.556 usec sync level 40 +/- 1 ire horizontal blanking rise time 10% - 90% 140 +/- 20 nsec sync rise time 10% - 90% 140 +/- 20 nsec burst envelope rise time 10% - 90% 300 +200 -100 nsec h-blanking start to h-reference 50% 1.5 +/- 0.1 usec horizontal sync 50% 4.7 +/- 0.1 usec horizontal reference point to burst start 50% 19 defined by sc/h cycles h reference to h-blanking end 50% 9.2 + 0.2 - 0.1 usec burst * ? 50% 9 +/- 1 cycles burst height ** 40 +/- 1 ire * measurement of burst timing length is made between the burst start point which is defined as the zero-cross point, preceding the first-half cycle of the sub-carrier w here burst amplitude becomes higher than 50 % level and the burst end point, defined in the same manner. burst time length ( period ) is 10 cycles in ntsc-4.43 mode. ** burst height of pal-m mode is 306 mv. 9 cycles 19 cycles +/-10 50% fig. 162 ntsc color burst
[AK8826VN] ms0972-e-01 113 2008/12 (1-2-1) vertical sync signal timing (ntsc/ntsc4.43) 3h 3h 1 2 3 4 5 6 7 89 0.5h 3h 19 +1/- 2line ( ?to
? ) 3h 3h 263 264 0.5h 3h 265 266 267 268 269 270 271 272 273 19 283 a b c d e f fig. 163 symbol duration measurement point reference a 429t b 858t c 31t d 429t e 858t f 63t 50% 13.5mhz clock equalizing pulse serration pulse g h 286mv i i i i fig. 164 equalizing pulse and serration pulse symbol measurement point value recommended tolerance units field period (derived) 16.6833 msec frame period (derived) 33.3667 msec vertical blanking start before first equalizing pulse 50% 1.5 +/- 0.1 usec vertical blanking (63.556usec x 20lines + 1.5usec) 19* lines + 1.5 usec 0 +/- 0.1 lines usec pre-equalizing duration 3 lines g pre-equalizing pulse width 50% 2.3 +/- 0.1 usec vertical sync duration 3 lines h vertical serration pulse width 50% 4.7 +/- 0.1 usec post-equalizing duration 3 lines g post-equalizing pulse width 50% 2.3 +/- 0.1 usec i sync rise time 140 +/- 20 nsec * there is a case with v-blank of 20 lines . this value is pre-settable by register.
[AK8826VN] ms0972-e-01 114 2008/12 (1-2-2) vertical sync signal timing and burst phase (pal-m) a b 523 524 525 123 4 56 8 7 910 522 521 520 519 a b 263 264 265 266 267 268 270 269 271 272 261 262 260 259 258 257 a b 523 524 525 123 4 56 8 7 910 522 521 520 519 263 264 265 266 267 268 270 269 271 272 261 262 260 259 258 257 a b fig. 165 a: phase of burst: nominal value + 135 b: phase of burst : nominal value - 135
[AK8826VN] ms0972-e-01 115 2008/12 (2-1) pal-b,d,g,h,i,n / pal-60 ( sd block control register [sdvm3:sdvm2]-bit = 11) 90% 50% 10% 90% 50% 10% 50% horizontal blanking rise tim e sync rise time h reference to blanking end horizontal sync horizontal reference point h blanking start to h -reference 50% sync level 90% 10% h . re f. to b u rst sta rt burst envelope rise tim e 50% burst height burst fig. 166 measurement point value recommended tolerance units total line period(derived) 64.0 usec sync level 300 mv horizontal blanking rise time 10% - 90% 0.3 +/- 0.1 usec sync rise time 10% - 90% 0.2 +/- 0.1 usec burst envelope rise time 10% - 90% nsec h-blanking start to h-reference 50% 1.5 +/- 0.3 usec horizontal sync 50% 4.7 +/- 0.2 usec horizontal reference point to burst start 50% 19 defined by sc/h cycles h reference to h-blanking end 50% 10.5 usec burst * ? 50% 10 +/- 1 cycles burst height ** 300 mv
[AK8826VN] ms0972-e-01 116 2008/12 (2-2) vertical sync signal timing and burst phase pal-b,d,g,h,i,n / pal-60 ( sd block control register [sdvm3:sdvm2]-bit = 11) 313 314 315 316 317 318 320 319 321 322 311 312 310 309 308 a b 313 314 315 316 317 318 320 319 321 322 311 312 310 309 308 a b a b 623 624 625 123 4 56 8 7 622 621 620 ab 623 624 625 123 4 56 8 7 622 621 620 fig. 167 a: phase of burst: nominal value + 135 b: phase of burst: nominal value - 135
[AK8826VN] ms0972-e-01 117 2008/12 video id the ak8826 supports to encode the video id (eiaj cpr-1204) which distinguishes the aspect ratio etc... this is also used as cgms (copy generation management system). turning ?on / off ?of this function is controlled by sdvbid-bit of sd/hd v-blanking control register (r/w) [sub address 0x12] and setting data is set by sd vbid-a data1/data2 register ( 0x2a, 0x2b ) . as for the video id setting for component video encoder mode is described in another section. vbid data up-date timing vsync new data data old data new data u-p data set control register fig. 168 vbid data code assignment 20 bit data is configured with word0 = 2 bits, word1 = 4 bits, word2 = 8 bits, crc = 6 bits. crc is automatically calcul ated and added in the ak8826. default values of ?crc polynomial ex pression x6 + x + 1? are all ones. bit1 bit20 data word0 2bit word1 4bit word2 8bit crc 6bit vbid waveform ref. bit1 bit2 bit3 bit20 ??? 2.235usec +/- 50nsec 11.2usec +/- 0.3usec 49.1usec +/- 0.44usec 1h 70ire +/- 10ire 0ire + 10 ire ? 5 ire fig. 169 525/60 system amplitude 70ire encode line 20/283
[AK8826VN] ms0972-e-01 118 2008/12 closed caption the description about ?closed caption? is wri tten in [6. common function specification]. wss the description about ?wss? is written in [6. common function specification].
[AK8826VN] ms0972-e-01 119 2008/12 9. high speed video dac mode block diagram dat a hdi vdi delay (+/-3clk) level converter dac hdo vdo fig. 170 high speed video dac mode input data format input data output operation rgb565 analog rgb digital rgb data is converted to analog rgb signal by dac rgb666 analog rgb digital rgb data is converted to analog rgb signal by dac full-scale code and level conversion input data is expanded to 10-bit, then it is converted to analog signal with dac. full-scale code is shown as following table. rgb565 rgb666 full-scale code r=0x3e0 g=0x3f0 b=0x3e0 r=0x3f0 g=0x3f0 b=0x3f0 the dac output level at full-scale code can be set with olvl-bit of dac control register [subaddress 0x0d] . dac control register sub address 0x0d default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved olvl dtrstn cvbssel dac3en dac2en dac1en olvl-ibit output level [v] 0 1.28v (typ) 1 0.7v (typ)
[AK8826VN] ms0972-e-01 120 2008/12 delay function for input timing signal input timing signal can be delayed by setting register. amount of adjustment is +/- 3-clock. delay adjustment is controled by video dac delay control register [subaddress0x51] . video dac delay control register sub address 0x51 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved resrved hdly2 hdly1 hdly0 amount of delay is set wit 2?s compriment. hdly[2:0]-bit delay 000 delay 0 001 1clk delay 010 2clk delay 011 3clk delay 111 1clk advanced 110 2clk advanced 101 3clk advanced
[AK8826VN] ms0972-e-01 121 2008/12 10. ak8826 register definition register map sub- address register default r/w function 0x00 hd mode register 0x00 r/w component video encoder setting 0x01 hd vbi & clip level control register 0x04 r/w setting for vbi intervale & clip 0x02 hdypbpr delay control register 0x00 r/w d elay adjustment for component video block 0x03 hd vbid data 1 register 0x00 r/w 0x04 hd vbid data 2 register 0x00 r/w vbid data setting reigster 0x05 reserved register 0x00 r/w 0x06 powerdown mode register 0x00 r/w setting for power down 0x07 hd block control register 0x00 r/w 0x08 hd wss data 1 register 0x00 r/w 0x09 hd wss data 2 register 0x00 r/w wss data register for component video encoder 0x0a hd block miscellaneous control register 0x00 r/w control register for component video encoder 0x0b i/o data format register 0x00 r/w setting i/o data format 0x0c i/o pin control register 0x00 r/w setting i/o pin configration 0x0d dac control register 0x00 r/w control dac 0x10 sd blanking set register 0xa1 r/w setting vbi interval for composite video encoder 0x11 sd block control register 0x10 r/w control regsiter for composite video encoder mode 0x12 sd/hd v-blanking control register 0x00 r/w setting vbi interval signal 0x13 sd block delay register 0x00 r/w delay control register for composite video encoder 0x14 sd block flt register 0x00 r/w setting luminance filter 0x15 reserve register 0x00 r/w 0x16 sub carrier frequency control register 0x00 r/w adjust subcarrier frequency 0x17 sub carrier phase control register 0x00 r/w adjust subcarrier phase. 0x18 sd wss data 1 register 0x00 r/w 0x19 sd wss data 2 register 0x00 r/w wss data register for wss 0x1a reserved 0x0f r/w 0x1b reserved 0xfc r/w 0x1c reserved 0x20 r/w 0x1d reserved 0xd0 r/w 0x1e reserved 0x6f r/w 0x1f reserved 0x0f r/w 0x20 reserved 0x00 r/w 0x21 reserved 0x00 r/w 0x22 reserved 0x0c r/w 0x23 reserved 0xf3 r/w 0x24 reserved 0x09 r/w 0x25 0x00 r/w reserved register 0x26 closed caption data 1 register 0x00 r/w 0x27 closed caption data 2 register 0x00 r/w closed caption data set-register for composite video encoder block 0x28 cc extended data 1 register 0x00 r/w 0x29 cc extended data 2 register 0x00 r/w closed caption extended data set-register for composite video encoder block 0x2a sd vbid-a data1 register 0x00 r/w 0x2b sd vbid-a data2 register 0x00 r/w vbid data set-register for composite video encoder block 0x2c 0x2d reserved 0xe3 r/w 0x2e reserved 0xbd r/w 0x2f reserved 0x66 r/w 0x30 reserved 0xb5 r/w 0x31 reserved 0x90 r/w 0x32 reserved 0xb2 r/w 0x33 reserved 0x7d r/w reserved register 0x34 status register 0x00 r status register 0x35 device id & revision id register 0x25 r device id and revision id register
[AK8826VN] ms0972-e-01 122 2008/12 0x38 test register 1 0x00 r/w test register 0x39 test regster 2 0x00 r/w test register 0x3a test regster 3 0x00 r/w test register 0x3b test regster 4 0x00 r/w test register 0x3c test regster 5 0x00 r/w test register 0x3d test regster 6 0x00 r/w test register 0x3e test regster 7 0x00 r/w test register 0x3f test regster 8 0x00 r/w test register 0x40 vbid-b header data register 0x08 r/w setting vbid header 0x41 vbid-b version number register 0x00 r/w settingvbid version number 0x42 vbid-b payload packet length register 0x00 r/w setting vbid packet length 0x43 vbid-b payload data1 register 0x00 r/w setting vibd payload data 0x44 vbid-b payload data2 register 0x00 r/w setting vibd payload data 0x45 vbid-b payload data3 register 0x00 r/w setting vibd payload data 0x46 vbid-b payload data4 register 0x00 r/w setting vibd payload data 0x47 vbid-b payload data5 register 0x00 r/w setting vibd payload data 0x48 vbid-b payload data6 register 0x00 r/w setting vibd payload data 0x49 vbid-b payload data7 register 0x00 r/w setting vibd payload data 0x4a vbid-b payload data8 register 0x00 r/w setting vibd payload data 0x4b vbid-b payload data9 register 0x00 r/w setting vibd payload data 0x4c vbid-b payload data10 register 0x00 r/w setting vibd payload data 0x4d vbid-b payload data11 register 0x00 r/w setting vibd payload data 0x4e vbid-b payload data12 register 0x00 r/w setting vibd payload data 0x4f vbid-b payload data13 register 0x00 r/w setting vibd payload data 0x50 vbid-b payload data14 register 0x00 r/w setting vibd payload data 0x51 video dac delay control register 0x00 r/w delay control regsiter for high speed dac mode * write default values (0x00) to test register(test register 1 to test register 8), if it is necessary to access these register s.
[AK8826VN] ms0972-e-01 123 2008/12 hd mode register (r/w) [sub address 0x00] [component video encoder] register to set the ak8826 mode at component video encoder mode sub address 0x00 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdcbg hdbbg hdsetup hdeavdec hdcea861 hdmode1 hdmode0 hdrfrsh default value 0 0 0 0 0 0 0 0 hd mode register (r/w) [sub address 0x00] bit register name r/w definition bit 0 hdrfrsh refresh rate bit r/w to select refresh rate 0 : 60hz 1 : 50hz bit1 ~ bit2 hdmode0 ~ hdmode1 mode set bit r/w to select input / output signals [hdmode1:hdmode0] 00 : 525i/625i 01 : 525p/625p 10 : 1080i 11 : 720p bit3 hdcea861 h/v timing std bit r/w to appoint relation when to synchronize with hsync / vsync 0: data capture is done by the ak8826 timing. 1: it is done by the compatible timing specified in cea 861b. when eavdec: 1, this bit is ignored. bit 4 hdeavdec eav decode bit r/w to select the ak8826 sync mode 0 : to be synchronized with hsync / vsync signals 1 : to be synchronized with eav bit 5 hdsetup hd setup-bit r/w to set on / off of 7.5 % set-up 0: no set-up process is done. 1: set-up process is done. bit 6 hdbbg hd black burst bit r/w to output black burst signal ( sync signal output only ) 0 : normal output 1: black burst signal output is enabled. bit 7 hdcbg hd color bar bit r/w to output color bar signal 0 : normal output 1: color bar signal is output. when hdbb bit is set, hdbb is prioritized.
[AK8826VN] ms0972-e-01 124 2008/12 hd vbi & clip level control register (r/w) [sub address 0x01] [component video encoder] vbi, clipping level of output is set. sub address 0x01 default value 0x04 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdclplvl1 hdclplvl0 reserved reserved reserved hdvunmsk hdvl1 hdvl0 default value 0 0 0 0 0 1 0 0 hd vbi & clip level control register (r/w) [sub address 0x01] bit register name r/w definition bit 0 ~ bit 1 hdvl0 ~ hdvl1 hd vb setting r/w adjust vbi blanking lines. final lines of the blanking period are adjusted. values are relative number of the default line (line 20). [hdvl1:hdvl0]-bit 01:increased by 1 line 00: default 11: decreased by 1 line. 10: decreased by 2 lines. bit 2 hdvunmsk v-blank unmask bit r/w sets the masking action during v-blanking periods. 0 : during v-blanking outputs are masked. black is outputs 1: normal operation. (input data is output during v-blanking periods.) following lines are in the interest. 525i : 10 - 20(+/-vl[1:0]) and 273- 283(+/-vl[1:0]) line 525p : 13 - 42(+/-vl[1:0]) line 1080i : 7 - 20(+/-vl[1:0]) line and 569 - 583(+/-vl[1:0]) line 720p : 6 - 24(+/-vl[1:0]) lien bit 3 ~ bit 5 reserved reserved bit r/w reserved, write 0x00 bit 6 ~ bit 7 hdclplvl0 ~ hdclplvl1 hd clamp level bit r/w define clipping level of the over sampling filter. [hdclplvl1:hdclplvl0] = 00:no clipping 01: clips at about -7.0 ire below pedestal level. 10: clips at about -1.5 ire below pedestal level. 11:reserved
[AK8826VN] ms0972-e-01 125 2008/12 hdypbpr delay control register (r/w) [sub address 0x02] ? [component video encoder] delay amounts of y signal and pb / pr signals are set. sub address 0x02 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved pbprdly2 pbprdly1 pbprdly0 reserved hdydelay2 hdydealy1 hdydelay0 default value 0 0 0 0 0 0 0 0 hdypbpr delay control register (r/w) [sub address 0x02] bit register name r/w definition bit 0 ~ bit 2 hdydelay0 ~ hdydelay2 hdy delay set bits r/w luminance signal delay amount is set. it is a delay from sync signal. delay amount is set based on 27 mhz clock in 480i / p modes, and 74.25 mhz in 1080i / 720p modes. [ hdydelay2 : ydelay1 ] - bit 000 : delay amount 0 001: 1 clk time is delayed. 010: 2 clk time is delayed. 011: 3 clk time is delayed. 111: advance 1 clk time to output. 110: advance 2 clk time to output. 101: advance 3 clk time to output. 100 : reserved bit 3 reserved reserved bit r/w reserved, write ?0 ?. bit 4 ~ bit 6 pbprdly0 ~ pbprdly2 c delay set bits r/w chroma signal delay amount is set. it is a delay from luminance signal. delay amount is set, based on 27 mhz clock in 480i/p modes, and 74.25 mhz in 1080i / 720p modes. both pb / pr are delayed by same amount by delay amount setting. [ pbprdly2 : pbprdly0 ] ? bit 000: delay amount 0 001: 1 clk time is delayed. 010: 2 clk time is delayed. 011: 3 clk time is delayed. 111: advance 1 clk time to output. 110: advance 2 clk time to output. 101: advance 3 clk time to output. 100: reserved bit 7 reserved reserved bit r/w reserved, write ?0 ?.
[AK8826VN] ms0972-e-01 126 2008/12 hd vbid data 1 register (r/w) [address 0x03] hd vbid data 2 register (r/w) [address 0x04] [component video encoder] registers to set cgms-a data cgms-a data is set. crcc data is automatically generated and added. address 0x03 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdvbiden reserved hdvbid1 hdvbid2 hdvbid3 hdvbid4 hdvbid5 hdvbid6 default value 0 0 0 0 0 0 0 0 address 0x04 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdvbid7 hdvbid8 hdvbid9 hdvbid10 hdvbid11 hdvbid12 hdvbid13 hdvbid14 default value 0 0 0 0 0 0 0 0 hd vbid data 1 register (r/w) [address 0x03] bit register name r/w definition bit 0 ~ bit 5 hdvbid6 ~ hdvbid1 vbid data bit r/w vbid (cgms-a) data is set. data to be set are cgms1 ~ cgms6. cgms7 ~ cgms14 should be set at cgms data 2 register. bit 6 reserved reserved bit r/w reserve, write ?0 ?. bit 7 hdvbiden vbid enable bit r/w this bit is set when vbid (cgms-a) signal is to be super-imposed. target line to be super-imposed with, is automatically decided by setting [ hdmode1 : hdmode0 ]-bits for hdmode register. 0: cgms-a function is ?off ?. 1: cgms-a signal is super-imposed. hd vbid data 2 register (r/w) [address 0x04 bit register name r/w definition bit 0 ~ bit 7 hdvbid14 ~ hdvbid7 vbid data bit r/w vbid (cgms-a) data is set. data to be set are cgms7 ~ cgms14. cgms1 ~ cgms6 should be set at cgms data 1 register. - about outputting cgms data write operation of cgms data via i2c interface must be comp leted by the time when the preceding 2 lines are completed, from a target output line. each line starts at eav.
[AK8826VN] ms0972-e-01 127 2008/12 reserved register (r/w) [sub address 0x05] ? reserve register sub address 0x05 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved reserved reserved default value 0 0 0 0 0 0 0 0 reserved register (r/w) [sub address 0x05] bit register name r/w definition bit 0 ~ bit 7 reserved reserved bit r/w reserve, write ?0x00 ?.
[AK8826VN] ms0972-e-01 128 2008/12 powerdown mode register (r/w) [sub address 0x06] ? [common register for all function block] to set power-down and operation modes of the ak8826. sub address 0x06 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved pllpdn slpen1 slpen0 default value 0 0 0 0 0 0 0 0 bit register name r/w definition bit 0 ~ bit 1 slpen0 ~ slpen1 sleep enable bit r/w to control operation of sd / hd blocks ( digital portion ) [ slpen1 : slpen0 ]-bit 00: both sd /hd blocks are enabled. 01: hd block only is enabled. 10: sd block only is enabled. 11: entire device is put into power-down mode. bit 2 pllpdn pll power down bit r/w to control power-down of pll 0 : power down 1 : release from power-down bit 3 ~ bit 6 reserved reserved bit r/w reserved, write ?0 ?.
[AK8826VN] ms0972-e-01 129 2008/12 hd block control register (r/w) [sub a ddress 0x07] [component video encoder] to set miscellaneous function to register sub address 0x07 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdwss hdcflt1 hdcflt0 hdyflt1 hdyflt0 reserved colsncen hdvratio default value 0 0 0 0 0 0 0 0 hd block control register bit register name r/w definition bit 0 hdvratio video ratio bit r/w 286 / 714 ratio video signal is output at d1 / 60hz operation. 0 : 300 / 700 ratio video signal is output (770.2-a) 1 : 286 / 714 ratio video signal is output (770.1-a) bit 1 colsncen color sync enable bit r/w to add sync signal on pb/pr signal. 0: no sync on pb/pr signal 1: sync on pb/pr signal bit 2 reserved reserved-bit r/w reserved, write ?0 ?. bit3 ~ bit4 hdyflt0 ~ hdyflt1 hdy filter select r/w to select hdy video signal band limit filter [hdyflt 1: hdyflt 0] = 00 : normal 01 : mild 10 : soft 11 : normal bit5 ~ bit6 hdcflt0 ~ hdcflt1 hdpbpr filter select r/w to select hdpb / hdpr video signal band limit filter [hdcflt 1: hdcflt 0] = 00 : normal 01 : mild 10 : soft 11 : normal bit 7 hdwss wss set bit r/w to encode wss signal it is turned on only when d1/50hz is output 0 : wss off 1 : wss on
[AK8826VN] ms0972-e-01 130 2008/12 hd wss data 1 register (r/w) [sub address 0x08] hd wss data 2 register (r/w) [sub address 0x09] [component video encoder] register to set wss data sub address 0x08 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdg2-7 hdg2-6 hdg2- 5 hdg2-4 hdg1-3 hdg 1-2 hdg1-1 hdg1-0 default value 0 0 0 0 0 0 0 0 sub address 0x09 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved hdg4-13 hdg4- 12 hdg4-11 hdg3-10 hdg3-9 hdg3-8 default value 0 0 0 0 0 0 0 0 note) wss data is written in order of 0x08 and then 0x09. when the second byte (0x09) of wss data is written, the ak8826 interprets that data has been up-dated and it encodes the wss signal on the next video line (line23). data is retained till it is up-dated with a new one.
[AK8826VN] ms0972-e-01 131 2008/12 hd block miscellaneous control register (r/w) [sub address 0x0a] [component video encoder] to set miscellaneous function to register sub address 0x0a default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved std770_2c hdcea805b ccwsssue reserved hdaflt1 hdaflt0 default value 0 0 0 0 0 0 0 0 bit register name r/w definition bit 0 ~ bit 1 hdaflt0 ~ hdaflt1 hd aperture filter set bit r/w to set aperture compensation filter [aflt1:aflt0] 00: mode0 : less compensation (default) 01: mode1 10: mode2 11: mode3 : much compensation bit 2 reserved reserved r/w reserved, write ?0 ?. bit 3 ccwsssue cc, wss, setup enable bit r/w to set the set-up on the cc/wss line. 0: no set-up on cc/wss line. 1: 7.5% set-up is added on cc/wss line bit 4 hdcea805b cea 805b encode bit r/w to encode cea805b typeb data 0: no encoding typeb data 1: encoding typeb data bit 5 std770_2c cea 770.2-c bit r/w to adapt cea770.2-c standard 0: to adapt cea770.2.a standard 1: to adapt cea770.2.c standard bit 6 ~ bit 7 reserved reserved r/w reserved, write ?0 ?.
[AK8826VN] ms0972-e-01 132 2008/12 i/o data format register (r/w) [sub address 0x0b] [common register for all function block] to set input / output configuration sub address 0x0b default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hdsdmase yc2rgb reserved dtfmt convmod1 convmod0 inpfmt1 inpfmt0 default value 0 0 0 0 0 0 0 0 bit register name r/w definition bit 0 ~ bit 1 inpfmt0 ~ inpfmt1 input data format bit r/w to set input data bit width format [inpfmt1: inpfmt0] 00: 8bit data input 01: 16bit data input 10: 18bit data input 11: prohibited to set bit 2 ~ bit 3 convmod0 ~ convmod1 convert module select bit r/w to select encoding block convmod[1:0]= 00: to select composite video encoder block component video encoder block becomes sleep mode automatically. 01: to select component video encoder block composite video encoder block becomes sleep mode automatically. 10: to select high speed dac block composite video encoder block and component video encoder block becomes sleep mode automatically. 11: prohibited to set bit 4 dtfmt data format bit r/w to set input data format 0: ycbcr data 1: rgb data bit 5 reserved reserved bit r/w reserved, write ?0 ?. bit 6 yc2rgb ycbcr to rgb bit r/w to set ycbcr to rgb data conversion this mode only work at convmod[1:0]=01. 0: no conversion 1: ycbcr to rgb conversion is worked bit 7 hdsdmase hd/sd master mode enable bit r/w to set self-sync mode* in ca se of hdbbg-bit / hdcbg-bit / sdbbg-bit / sdcbg-bit is set. self-sync mode: working wit hout hd/vd and eav timing signal 0: no self-sync mode. 1: self-sync mode
[AK8826VN] ms0972-e-01 133 2008/12 i/o pin control register (r/w) [sub address 0x0c] [common register for all function block] to set the attribute of i/o pins. sub address 0x0c default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vdoen hdoen vdi_inv hdi_inv reserved vdopol hdopol clkinv default value 0 0 0 0 0 0 0 0 bit register name r/w definition bit 0 clkinv clock invert -bit r/w to set polarity of clock for clkin pin 0: capturing the data at the rising edge of clock 1: capturing the data at the falling edge of clock bit 1 hdopol hdo polarity bit r/w to set polarity of hdo 0: same polarity as input data. 1: inverted polarity as input data bit 2 vdopol vdo polarity bit r/w to set polarity of vdo 0: same polarity as input data. 1: inverted polarity as input data bit 3 reserved reserved r/w reserved, write ?0 ?. bit 4 hdi_inv hd polarity select r/w to set polarity of hdi 0 : active lo 1 : active high bit 5 vdi_inv vd polarity select r/w to set polarity of vdi 0 : active lo 1 : active high bit 6 hdoen hdo output enable bit r/w to control hdo 0: disable to output the timing signal from hdo 1: enable to output the timing signal from hdo bit 7 vdoen vdo ? output enable bit r/w to control vdo 0: disable to output the timing signal from vdo 1: enable to output the timing signal from vdo
[AK8826VN] ms0972-e-01 134 2008/12 dac control register(r/w) [sub address 0x0d] [common register for all function block] to set on / off of dacs sub address 0x0d default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved olvl dtrstn cvbssel dac3en dac2en dac1en default value 0 0 0 0 0 0 0 0 bit register name r/w definition bit 0 dac1en dac1 enable bit r/w to control dac1 on/off 0: off (output pin is hi-z states) 1: on bit 1 dac2en dac2 enable bit r/w to control dac2 on/off 0: off (output pin is hi-z states) 1: on bit 2 dac3en dac3 enable bit r/w to control dac3 on/off 0: off (output pin is hi-z states) 1: on bit 3 cvbssel cvbs select bit r/w to select the dac for cvbs output 0: dac3 outputs cvbs 1: dac1 outputs cvbs bit 4 dtrstn data clear bit r/w to reset all block 0: initialize the circuit 1: to release initialized states bit 5 olvl output level bit r/w to control dac output level this bit is valid at high speed dac mode. 0: to output about 1.28v at 0xff code. 1: to output about 0.7v at 0xff code. bit 6 ~ bit 7 reserved reserved bit r/w reserved, write ?0 ?.
[AK8826VN] ms0972-e-01 135 2008/12 sd blanking set register (r/w) [sub address 0x10] [composite video encoder block] to set ak8826 interface mode and v-blanking length at composite video encoder mode. sub address 0x10 default value 0xa1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sdbln4 sdbln3 sdbln2 sdbln1 sdbln0 reserved reserved rec656 default value 1 0 1 0 0 0 0 1 bit register name r/w definition bit 0 rec656 rec 656 bit r/w set this bit when to synchronize with itu-r. bt.656 ( compatible ) eav. 0 : eva is not decoded ( in case of synchronization with hsync / vsync ) 1: eva is decoded and the timing is synchronized with it. bit 1 ~ bit 2 reserved reserved bit r/w reserved, write ?0 ?. bit 3 ~ bit 7 sdbln0 ~ sdbln4 sd blanking line no. r/w to set line blanking output.
[AK8826VN] ms0972-e-01 136 2008/12 sd block control register (r/w) [sub address 0x11] [composite video encoder block] to set output signals sub address 0x11 default value 0x10 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sdbbg sdcbg sdsetup scr sdvm3 sdvm2 sdvm1 sdvm0 default value 0 0 0 1 0 0 0 0 bit register name r/w definition bit 0 ~ bit 3 sdvm0 ~ sdvm3 video mode 0 register ~ video mode 3 register r/w [ sdvm1 : sdvm0 ] ? bit 00 : 3.57954545 mhz 01 : 3.57561188 mhz 10 : 3.5820558 mhz 11 : 4.43361875 mhz [ sdvm3 : sdvm2 ] ? bit 00 : 525 / 60 01: 525 / 60 pal (pal-m etc...) 10 : reserved 11 : 625 / 50 pal ( pal-b, d, g, h, i, n ) bit 4 scr sub carrier reset bit r/w to set enable / disable reset of sub-carrier for each color sequence 0: no sub-carrier reset is done. 1: sub-carrier reset is enabled. ntsc: reset at every 2 frames. pal: reset at every 4 frames. bit 5 sdsetup sd setup-bit r/w to set the set-up 0 : no set-up 1: 7.5 % set-up is added. even when the set-up is turned on, set-up (pedestal) is not added while blanking line is being output. bit 6 sdcbg sd color bar generator control bit r/w setting bit of on-chip color bar 0: input data is encoded. 1: on-chip color bar is output. when sdbbg bit is set, sdbbg is prioritized. bit 7 sdbbg sd black burst generator control bit r/w black burst generator bit to output black burst signal 0: input data is encoded. 1: black burst signal is output. even when sdcbg bit is set, sdbbg is prioritized. sdvm3 ? sdvm0 settings for each standard are as follows. sdvm3:sdvm0 ntsc 0000 pal-b,d,g,h,i 1111 pal-m 0101 pal-60 0111 ntsc-4.43 0011
[AK8826VN] ms0972-e-01 137 2008/12 sd/hd v-blanking control register (r/w) [sub address 0x12] [composite video encoder / component video encoder block] to set v-blanking interval output data sub address 0x12 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved sdwss sdhdcc284 sdhdcc21 sdvbid default value 0 0 0 0 0 0 0 0 bit register name r/w definition bit 0 sdvbid sd video id bit r/w to set vbid data for composite video encoder mode/ 0: vbid off 1: vbid on bit 1 sdhdcc21 closed caption bit r/w to make closed caption signal enable for composite video encoder and component video encoder mode. 0: off 1: on bit 2 sdhdcc284 closed caption extended data bit r/w to make closed caption extended signal enable for composite video encoder and component video encoder mode. 0: off 1: on bit 3 sdwss wss set bit r/w to make wss enable for composite video encoder. 0: off 1: on bit 4 ~ bit 7 reserved reserved bit r/w reserved, write ?0 ?.
[AK8826VN] ms0972-e-01 138 2008/12 sd block delay register (r/w) [sub address 0x13] [composite video encoder block] to adjust yc delay amount of output signal sub address 0x13 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sdclplvl1 sdclplvl0 syd2 syd1 syd0 reserved reserved reserved default value 0 0 0 0 0 0 0 0 bit register name r/w definition bit 0 ~ bit 2 reserved reserved bit r/w reserved, write ?0 ?. bit 3 ~ bit 5 syd0 ~ syd2 s-video y delay bit r/w [[ syd2 : syd0 ] ? bit 101: y component output advances 3 clock times to c component. 110: y component output advances 2 clock times to c component. 111: y component output advances 1 clock time to c component. 000 : no delay between y component and c component 001 : y component output is delayed by 1 clock time to c component. 010 : y component output is delayed by 2 clock time to c component. 011 : y component output is delayed by 3 clock time to c component. bit 6 ~ bit 7 sdclplvl0 ~ sdclplvl1 sd clip level set bit r/w to clip the under-shoot of the over-sampling filter outputs to a pre-set value. [ sdclplvl1:sdclplvl1 ] 00: no clipping 01: to be clipped at approximately - 7.0ire 10: to be clipped at approximately -1.5ire 11: reserved
[AK8826VN] ms0972-e-01 139 2008/12 sd block flt register (r/w) [sub address 0x14] [composite video encoder block] to set band limit filter. sub address 0x14 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved sdyflt1 sdyflt0 reserved reserved reserved default value 0 0 0 0 0 0 0 0 bit register name r/w definition bit 0 ~ bit 2 reserved reserved bit r/w reserved, write ?0 ?. bit 3 ~ bit 4 sdyflt0 ~ sdyflt1 sdy filter select bit r/w to set sdy video signal band limit filter [sdyflt1:sdyflt0]= 00: normal 01: mild 10: soft 11: inhibited bit 5 ~ bit 7 reserved reserved r/w reserved, write ?0 ?.
[AK8826VN] ms0972-e-01 140 2008/12 reserve register (r/w) [sub address 0x15] [composite video encoder] reserved register sub address 0x15 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved reserved reserved default value 0 0 0 0 0 0 0 0 bit register name r/w definition bit 0 ~ bit 7 reserved reserved bit r/w reserved, write ?0 ?.
[AK8826VN] ms0972-e-01 141 2008/12 sub carrier frequency control register (r/w) [sub address 0x16] [composite video encoder] to set subcarrier frequency sub address 0x16 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 subf7 subf6 subf5 subf4 subf3 subf2 subf1 subf0 default value 0 0 0 0 0 0 0 0 bit register name r/w definition bit 0 ~ bit 7 subf0 ~ subf7 sub carrier frequency control bit r/w to fine-tune the sub-carrier frequency adjustment can be done, ranging from + 127 to _ 128 and adjustable step is in 0.8 hz / step.
[AK8826VN] ms0972-e-01 142 2008/12 sub carrier phase control register (r/w) [sub address 0x17] [composite video encoder] to set subcarrier phase sub address 0x17 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 subp7 subp6 subp5 subp4 subp3 subp2 subp1 subp0 default value 0 0 0 0 0 0 0 0 bit register name r/w definition bit 0 ~ bit 7 subp0 ~ subp7 sub carrier phase control bit r/w bit 0 ~ bit 7 sub-carrier phase control bits to set default value of sub-carrier phase adjustable step: 360 / 255 [deg.] sub-carrier phase is set at _ 180 degrees at default condition. phase rotates counter-clockwise to the set value.
[AK8826VN] ms0972-e-01 143 2008/12 sd wss data 1 register (r/w) [sub address 0x18] sd wss data 2 register (r/w) [sub address 0x19] [composite video encoder] to set wss data for composite video encoder mode sub address 0x18 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sdg2-7 sdg2-6 sdg2-5 sdg2-4 sdg1-3 sdg1-2 sdg1-1 sdg1-0 default value 0 0 0 0 0 0 0 0 sub address 0x19 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved sdg4-13 sdg4-12 sdg4-11 sdg3-10 sdg3-9 sdg3-8 default value 0 0 0 0 0 0 0 0 note) wss data is written in order of 0x18 and then 0x19. when the second byte (0x19) of wss data is written, the ak8826 interprets that data has been up-dated and it encodes the data on the next video line (line 23). data is retained till it is up-dated with a new one.
[AK8826VN] ms0972-e-01 144 2008/12 closed caption data 1 register (r/w) [sub address 0x26] closed caption data 2 register (r/w) [sub address 0x27] [component video encoder/ composite video encoder block] to set closed caption data sub address 0x26 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cc7 cc6 cc5 cc4 cc3 cc2 cc1 cc0 default value 0 0 0 0 0 0 0 0 sub address 0x27 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cc15 cc14 cc13 cc12 cc11 cc10 cc9 cc8 default value 0 0 0 0 0 0 0 0 note) closed caption data is written in order of 0x26 and then 0x27. when the second byte (0x27) of closed caption data is written, the ak8826 interprets that data has been up-dated and it encodes the data on the next video line. null codes are automatically output on those, not-data-updated lines. it is assumed that parity bit of each byte data is added by the host side.
[AK8826VN] ms0972-e-01 145 2008/12 cc extended data 1 register (r/w) [sub address 0x28] cc extended data 2 register (r/w) [sub address 0x29] [component video encoder/ composite video encoder block] to set closed caption extended data sub address 0x28 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ext7 ext6 ext5 ext4 ext3 ext2 ext1 ext0 default value 0 0 0 0 0 0 0 0 sub address 0x29 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ext15 ext14 ext13 ext12 ext11 ext10 ext9 ext8 default value 0 0 0 0 0 0 0 0 note) closed caption extended data is written in order of 0x28 and then 0x29. when the second byte (0x29) of closed caption extended data is written, the ak8826 interprets that data has been up-dated and it encodes the data on the next video line. null codes are automatically output on those, not-data-updated lines. it is assumed that parity bit of each byte data is added by the host side.
[AK8826VN] ms0972-e-01 146 2008/12 sd vbid-a data1 register (r/w) [sub address 0x2a] ? sd vbid-a data2 register (r/w) [sub address 0x2b] ? [composite video encoder block] to set vbid-a data sub address 0x2a default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved sdvbid1 sdvbid2 sdvbid3 sdvbid4 sdvbid5 sdvbid6 default value 0 0 0 0 0 0 0 0 sub address 0x2b default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sdvbid7 sdvbid8 sdvbid9 sdvbid10 sdvbid11 sdvbid12 sdvbid13 sdvbid14 default value 0 0 0 0 0 0 0 0 note) write ?0 ?to reserved bits. vbid1 ~ vbid14 correspond to bit 1 ~ bit 14 which are described at {vbid data code assignment} diagram at item { video id }. a 6 bit crc code from bit 15 ~ bit 20 is automatically added by the ak8826. data is retained till it is up-dated with a new one.
[AK8826VN] ms0972-e-01 147 2008/12 status register (r) [sub address 0x34] to show status of the ak8826 sub address 0x34 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved en284 en21 bit register name r/w definition bit 0 en21 encode 21 bit r to indicate up-date timing of the closed-caption data when en21 bit is ?1 ?, the ak8826 waits for data input coming. this bit becomes ?0 ?after data is written at the second byte (0x27). bit 1 en284 encode 284 bit r to indicate up-date timing of the closed-caption extended data when en284 bit is ?1 ?, the ak8822 waits for data input coming. this bit becomes ?0 ?after data is written at the second byte (0x29). bit 2 ~ bit 7 reserved reserved bit r reserved bit write ?0 ?.
[AK8826VN] ms0972-e-01 148 2008/12 device id & revision id register (r) [sub address 0x35] to indicate the ak8826 device id and revision id sub address 0x35 default value 0x26 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rev1 rev0 dev5 dev4 dev3 dev2 dev1 dev0 0 0 1 0 0 1 1 0 bit register name r/w definition bit 0 ~ bit 5 dev0 ~ dev5 device id bit r to indicate device id 0x26 is assigned to the ak8826 bit 6 ~ bit 7 rev0 ~ rev1 revision id r to indicate revision id revision id is up-dated when a possible software modification is made. it starts at 0x00.
[AK8826VN] ms0972-e-01 149 2008/12 vbid-b header data register (r/w) [sub address 0x40] ? [component video encoder block] to set video id type-b header data sub address 0x40 default value 0x08 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved h5 h4 h3 h2 h1 h0 default value 0 0 0 0 1 0 0 0 vbid-b version number register (r/w) [sub address 0x41] ? [component video encoder block] to set video id type-b payload data sub address 0x41 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p7 p6 p5 p4 p3 p2 p1 p0 default value 0 0 0 0 0 0 0 0 vbid-b payload packet length register (r/w) [sub address 0x42] ? [component video encoder block] to set video id type-b payload data sub address 0x42 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p15 p14 p13 p12 p11 p10 p9 p8 default value 0 0 0 0 0 0 0 0
[AK8826VN] ms0972-e-01 150 2008/12 vbid-b data1 register (r/w) [sub address 0x43] - vbid-b data13 register (r/w) [sub address 0x2b] [component video encoder block] to set video id data. crc code is automatica lly appended by ak8826. the data is hold till new data is up-dated. vbid-b payload data1 register (r/w) [sub address 0x43] ? sub address 0x43 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p23 p22 p21 p20 p19 p18 p17 p16 default value 0 0 0 0 0 0 0 0 vbid-b payload data2 register (r/w) [sub address 0x44] ? sub address 0x44 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p31 p30 p29 p28 p27 p26 p25 p24 default value 0 0 0 0 0 0 0 0 vbid-b payload data3 register (r/w) [sub address 0x45] ? sub address 0x45 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p39 p38 p37 p36 p35 p34 p33 p32 default value 0 0 0 0 0 0 0 0 vbid-b payload data4 register (r/w) [sub address 0x46] sub address 0x46 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p47 p46 p45 p44 p43 p42 p41 p40 default value 0 0 0 0 0 0 0 0 vbid-b payload data5 register (r/w) [sub address 0x47] ? sub address 0x47 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p55 p54 p53 p52 p51 p50 p49 p48 default value 0 0 0 0 0 0 0 0 vbid-b payload data6 register (r/w) [sub address 0x48] ? sub address 0x48 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p63 p62 p61 p60 p59 p58 p57 p56 default value 0 0 0 0 0 0 0 0
[AK8826VN] ms0972-e-01 151 2008/12 vbid-b payload data7 register (r/w) [sub address 0x49] ? sub address 0x49 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p71 p70 p69 p68 p67 p66 p65 p64 default value 0 0 0 0 0 0 0 0 vbid-b payload data8 register (r/w) [sub address 0x4a] ? sub address 0x4a default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p79 p78 p77 p76 p75 p74 p73 p72 default value 0 0 0 0 0 0 0 0 vbid-b payload data9 register (r/w) [sub address 0x4b] ? sub address 0x4b default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p87 p86 p85 p84 p83 p82 p81 p80 default value 0 0 0 0 0 0 0 0 vbid-b payload data10 register (r/w) [sub address 0x4c] ? sub address 0x4c default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p95 p94 p93 p92 p91 p90 p89 p88 default value 0 0 0 0 0 0 0 0 vbid-b payload data11 register (r/w) [sub address 0x4d] ? sub address 0x4d default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p103 p102 p101 p100 p99 p98 p97 p96 default value 0 0 0 0 0 0 0 0 vbid-b payload data12 register (r/w) [sub address 0x4e] ? sub address 0x4e default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p111 p110 p109 p108 p107 p106 p105 p104 default value 0 0 0 0 0 0 0 0 vbid-b payload data13 register (r/w) [sub address 0x4f] ? sub address 0x4f default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p119 p118 p117 p116 p115 p114 p113 p112 default value 0 0 0 0 0 0 0 0 vbid-b payload data14 register (r/w) [sub address 0x50] ? sub address 0x50 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved reserved p121 p120 default value 0 0 0 0 0 0 0 0
[AK8826VN] ms0972-e-01 152 2008/12 video dac delay control register(r/w) [sub address 0x51] [high speed video dac mode] to set video dac delay sub address 0x51 default value 0x00 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved reserved hdly2 hdly1 hdly0 default value 0 0 0 0 0 0 0 0 bit register name r/w definition bit 0 ~ bit 2 hdly0 ~ hdly2 hd delay bit r/w to adjust hdi timing delay 000 : 3clk delay 001 : 2clk delay 010 : 1clk delay 011 : no delay 111 : 1clk advanced 110 : 2clk advanced 101 : 3clk advanced 100 : inhibited to set bit 3 ~ bit 7 reserved reserved r/w reserved, write ?0?
[AK8826VN] ms0972-e-01 153 2008/12 11. system connection example fig. 171 system connection example u- p mpeg decoder amp + lpf dac1 ? - dac2 ? - dac3 ? - scl 3.9k-ohm i 2 c bus ak8826 data[15:0] clkin 8 or 16 sela x 3ch pdn 0.1uf avdd vref hdi vdi sda gp io flt avdd bypass iref 300-ohm 75-ohm 4.7nf 820-ohm avss dvdd dvss avdd tmo test0 test1 pvdd2 pvdd1 pvdd2 digital 1.8v analog 3.0v data i/o power u-p i/o power 0.1uf 10uf 10uf 0.1uf 0.1uf
[AK8826VN] ms0972-e-01 154 2008/12 12. package 0.05 s 0.170.05 0.02 - 0.015 +0.02 0.920.08 s 0.25 +0.40 -0.15 0.170.05 0.350.12 12 13 48 25 24 37 36 1 45 45 3-0.50 +0.4 0 -0.15 0.50 7.200.10 7.000.05 7.200.10 7.000.05 c0.6 3-c0.2 0.220.05 0.05 m s ab a b 1 48 13 36 37 24 25 12 fig. 172 package (qfn48 7.2mm x 7.2mm)
[AK8826VN] ms0972-e-01 155 2008/12 13. marking 1 a km AK8826VN xxxxxxx a. pin type : qfn b. pin count : 48pin c. product number : 8826vn d. cont rol code : xxxxxxx (7 digits)
[AK8826VN] ms0972-e-01 156 2008/12 revised history ms0972-e-00 -> ms0972-e-01 package drawing and marking are changed. the numeric values in package drawing are not changed.
[AK8826VN] ms0972-e-01 157 2008/12 z these products and their specifications are subject to change without notice. when you consider any use or application of these pr oducts, please make inquir ies the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any pa tent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akemd products are neither intended nor authorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approv ed with the express written consen t by representative director of akemd. as used here: note1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which mu st therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for app lications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akemd products, who dist ributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributo r agrees to assume any and all responsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification. im portant notice

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